An overview and comparison of different topologies for wireless architectures are discussed, where the main focus lies on the power consumption and possibilities towards integration and reduction of external components. Architectures with reduced number of building blocks (both internal and external) are presented where the main benefits are the low costs, both in the CMOS technology as well as the power.

This paper describes an optimization technique able to optimize a complete wireless receiver architecture in a reasonable amount of time. The optimizer alternates between spice level optimizations of simple building blocks and a full architecture optimization of the whole based on accurate models of the building blocks. The models of the building blocks are interpolated over the data points acquired in the Spice level simulations. The optimizer technique has been applied to the optimization of an architecture for a GPS receiver. The optimal design has been implemented in a standard 0.25μm CMOS process.

In this paper a layout-aware RF synthesis methodology is presented. The methodology combines the power of a differential evolution algorithm with cost function response modeling and integrated layout generation to synthesize RF Circuits efficiently, taking into account all layout parasitics during the circuit optimization. The proposed approach has successfully been applied to the design of a high-performance downconverter mixer circuit, proving the effectiveness of the implemented design methodology.

This paper presents an automated, layout-aware RF LC-oscillator design tool, called CYCLONE that delivers an accurate and optimal LC-oscillator design, from specification to layout. The tool combines the accuracy of device-level simulation and finite element analysis with the optimisation power of simulated annealing algorithms and is verified with experimental results.

This paper presents an optimization algorithm that is able to significantly increase the speed of RF circuit optimizations.The algorithm consists of a series of consecutive evolutionary optimizations of the circuit itself and of a modeled version thereof.The speed increase arises from the difference in evaluation time between the real simulation and the fit evaluation.As circuit approximation, behavioral models are used instead of polynomial expressions, allowing to put some "design knowledge" into the optimization.gaRFeeld is a tool implementing this smart evolutionary algorithm for RF circuits.Finally some experiments performed with gaRFeeld are illustrated for the optimization of a Low Noise Amplifier.

An integrated tool called DAISY (Delta-Sigma Analysis and Synthesis) is presented for the high-level synthesis of /spl Delta//spl Sigma/ modulators. The approach determines both the optimum modulator topology and the required building block specifications, such that the system specifications mainly accuracy and signal bandwidth-are satisfied at the lowest possible power consumption. A genetic-based differential evolution algorithm is used in combination with a fast dedicated behavioral simulator that includes the major nonidealities of the building blocks to realistically analyze and optimize the modulator performance. Experimental results illustrate the effectiveness of the approach. Also, an overview of optimized topologies as a function of the modulator specifications for a wide range of values shows the capabilities and performance range covered by the tool.