It has recently become more difficult for packet processing switches, which have very high speed interface cards, to achieve rich Quality of Service (QoS) functions because such high-speed switches have insufficient packet processing times. In particular, the scheduler/shaper is one of the greatest hindrances to increasing the speed of processing because it selects a suitable queue based on complex algorithms (e.g., weighted round robin (WRR) or strict priority (SP)) in a limited time. One solution that mitigates this scheduling/shaping speed problem is burst packet processing. However, burst packet processing has several side effects. We analyze these side effects and propose a scheduling architecture that minimizes them. We also show the effectiveness of our proposed architecture based on simulation results.

GaAs FET amplifier modules for 20 GHz band satellite communications have been developed using newly developed power FETs. The deep recess gate structure was adopted in the power FET, which improved both power output capability and power gain. Power added efficiency of 22 percent with more than 1 W power output has been achieved with 3 mm gate width FETs. The amplifier modules containing two-stage internally matched FET's can be hermetically sealed in metal packages. The modules had 8.4-8.9 dB linear gain in the 17.7-18.8 GHz band and 7.9-8.4 dB linear gain in the 18.5-19.6 GHz band. The power output at 1 dB gain compression point was more than 0.5 W. The third-order intermodulation distortion ratio was 81-83 dB at 18.2 GHz and 77-80 dB at 18.9 GHz, when individual output signal power was -4 dBm.