The P4 community has recently put significant effort to increase the diversity of targets on which P4 programs can be implemented. These include fixed function and programmable ASICs, FPGAs, NICs, and CPUs. However, P4 programs are written according to the set of functionalities supported by the target for which they are compiled. For instance, a P4 program targeting a programmable ASIC cannot be extended with user-defined processing modules, which limits the flexibility and the abstraction of P4 programs. To address these shortcomings, we propose a heterogeneous P4 programmable data plane comprised of different targets that together appear as a single logical unit. The proposed data plane broadens the range of functionalities available to P4 programmers by combining the strength of each target. We demonstrate the feasibility of the proposed P4 data plane by coupling an FPGA with a soft switch which emulates a programmable ASIC. The proposed data plane is demonstrated with the implementation of a simplified L2 switch. The emulated ASIC match-table capacity is extended by the FPGA by an order of magnitude.The FPGA also integrates a proprietary module using a P4 extern.

Due to the rapid growth of traffic on the Internet, the IP lookup process imposes ever-growing performance requirements in order to avoid that it becomes a bottleneck during packet forwarding. This complex function is often implemented by hardware accelerators that are integrated with a processor. In this paper, we use a modified cache memory as an accelerator to perform IP lookup. Hashing is used for mapping each bucket of a hash table to a set of the cache memory. We show that, in the proposed scheme, a table of 26K prefixes fits into a cache of 1MB and the throughput achieved allows processing packets at wire speed over four 40Gb links.