Demo Data from SIGIR 2026 / reviewers in the wild / expert
Andy Newell
dblp:227/3191
· DBLP profile ↗
1ranked-venue papers
1as first author
0since 2021 · last 2020
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Software engineering, system software, and programming languages
1 paper |
Compilers and program optimization · 100% | |
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Memory systems · 100% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Compilers and program optimization
binary optimization |
0.4 | 1 | 2020 | Improved Basic Block Reordering · IEEE Trans. Computers 2020 |
Compilers and program optimization › binary rewriting
post-link optimization |
0.4 | 1 | 2020 | Improved Basic Block Reordering · IEEE Trans. Computers 2020 |
Compilers and program optimization › dynamic optimization
profile-guided optimization |
0.4 | 1 | 2020 | Improved Basic Block Reordering · IEEE Trans. Computers 2020 |
Memory systems
cache |
0.1 | 1 | 2020 | Improved Basic Block Reordering · IEEE Trans. Computers 2020 |
Memory systems › cache › CPU cache
instruction cache |
0.1 | 1 | 2020 | Improved Basic Block Reordering · IEEE Trans. Computers 2020 |
Methods — techniques the papers use, named apart from their topics
machine learning · 0.9
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2020 | Improved Basic Block ReorderingabstractBasic block reordering is an important step for profile-guided binary optimization. The state-of-the-art goal for basic block reordering is to maximize the number of fall-through branches. However, we demonstrate that such orderings may impose suboptimal performance on instruction and I-TLB caches. We propose a new algorithm that relies on a model combining the effects of fall-through and caching behavior. As details of modern processor caching is quite complex and often unknown, we show how to use machine learning in selecting parameters that best trade off different caching effects to maximize binary performance. An extensive evaluation on a variety of applications, including Facebook production workloads, the open-source compilers Clang and GCC, and SPEC CPU benchmarks, indicate that the new method outperforms existing block reordering techniques, improving the resulting performance of applications with large code size. We have open sourced the code of the new algorithm as a part of a post-link binary optimization tool, BOLT. Andy Newell, Sergey Pupyrev |
IEEE Trans. Computers | 1 |