Boseop Kim, HyoungSeok Kim, Sang-Woo Lee, Gichang Lee, Donghyun Kwak, Jeon Dong Hyeon, Sunghyun Park, Sungju Kim, Seonhoon Kim, Dongpil Seo, Heungsub Lee, Minyoung Jeong, Sungjae Lee, Minsub Kim, Suk Hyun Ko, Seokhun Kim, Taeyong Park, Jinuk Kim, Soyoung Kang, Na-Hyeon Ryu, Kang Min Yoo, Minsuk Chang, Soobin Suh, Sookyo In, Jinseong Park, Kyungduk Kim, Hiun Kim, Jisu Jeong, Yong Goo Yeo, Donghoon Ham, Dongju Park, Min Young Lee, Jaewook Kang, Inho Kang, Jung-Woo Ha, Woomyoung Park, Nako Sung. Proceedings of the 2021 Conference on Empirical Methods in Natural Language Processing. 2021.

This paper presents a logic resynthesizing of FPGA from a downloaded bitstream data for Xilinx 7 series FPGA. This study focuses on the LUT logic reconstructing, which is a primitive logic unit in FPGA. The approach generates all possible logic for a LUT trying to various examples. The generated files are compared with each other that are used to construct the truth table of the LUT. The proposed algorithm extracts the logic configuration by analyzing the bitstream and comparing it with the constructed truth table. The resynthesized circuits provide the input and output pin information assigned in the LUT. The algorithm can be expanded to the previous version of Xilinx 7 series. This study will be helpful for security enhancing of FPGA and development of logic synthesis technique.