This paper presents a technique for describing the behavior of transmission gates (TGs) in VHDL. The concept of virtual signal is introduced into the TG's data structure to represent the nature of the connection. The model's semantics are coded in three parts: the state transition, the steady states, and the connecting protocol. Simulation results indicate that the model is correct and robust.

Previous work on computer architecture design for robotics is reviewed. Based on the analysis of the performance data, two crucial issued are addressed: the decision on how specific an architecture should be and which architecture styles should be chosen for particular applications.>

ASIC (application-specific integrated circuit) technology has created opportunities for implementing robotic control algorithms directly in silicon. However, the sheer complexity of VLSI design represents a tremendous knowledge barrier to system designers. To lower this knowledge barrier, a concise conceptual framework is presented which allows robotics hardware designers to acquire the essential knowledge of the ASIC technology efficiently. It addresses different aspects of how design decisions are made. The global strategy is to limit the search space through methodology implemented by CAE (computer-aided engineering) and expert systems. Alternatives are recognized through a proper framing of design space. A set of techniques for evaluation of the alternatives is classified. The conceptual framework enables system designers and application engineers to acquire and apply ASIC technology in a systematic and logical manner and thus facilitates efficient application of the technology in robotic hardware designs.>

An attempt is made to gain a better understanding of the nature of ASIC (application-specific integrated circuit) design. This is done from a decision-making perspective, in terms of three knowledge frames: the design process, the design hyperspace, and the design repertoire. The design process frame emphasizes the hierarchical design approach and presents the methodology as a formalization of the design process. The design hyperspace concept relates to the recognition of design alternatives. Analysis techniques for evaluating algorithmic and architectural alternatives are collected and classified to form the design repertoire. This conceptual framework is an effective instrument for bridging the widening gap between system designers and VLSI technology. It also provides a conceptual platform for the development of tools for high-level architectural designs.>

A conceptual framework consisting of the design process, the design space, and the design repertoire for ASIC hardware is presented. An Inter-Level Design Process Model (ILDP) is proposed as a general model for expressing and implementing hierarchical design methodologies. The proposed conceptual framework is an effective instrument for bridging the increasingly wider gap between application engineers and VLSI designers.

The desire to add more intelligent functionality and enhanced real-time Control capability to robotic systems places a heavy demand on computational resources. Nascent application-specific VLSI technology offers an unprecedented opportunity to relieve this computational burden by implementing specific robotic functions directly in hardware. A VLSI architecture, designed to compute the direct kinematic solution (DKS) on a single chip, is described. The DKS chip features fixed-point calculation and on-chip generation of trigonometric functions. The calculation achieves the resolution required for most industrial applications. Innovative modifications of the conventional adder control and the form of the homogeneous transformation matrix have improved throughput. Simulation results indicate that speed improvements of several orders of magnitude in the kinematic computation are achievable with application-specific integrated circuit technology, compared to microprocessor implementation.

The architecture of a VLSI chip dedicated to the real-time computation of the Direct Kinematic Solution (DKS) is described. The design features fixed-point calculation and on-chip generation of trigonometric functions. The computed output has the resolution required for most industrial applications. Consideration of VLSI design regularity leads to the modification of the homogeneous transformation matrices. Pipelining techniques are applied to improve throughput. The control-store implementation provides adaptability to virtually all robot arms. Transistor and cell counts confirm the feasibility of a semi-custom implementation approach with current technology. Results indicate that the DKS can be obtained in microseconds with this new architecture, which amounts to a speed improvement of three orders of magnitude compared to a similar algorithm implemented on a 16-bit microprocessor.