The authors present a byte-interleaving architecture for generating higher-order signals in the synchronous optical network (SONET) digital hierarchy and report on the implementation and system performance results of an experimental 2.488 Gbit/s SONET STS-3c to STS-48 (OC-48) byte multiplexer/scrambler and STS-48 (OC-48) to STS-3c byte demultiplexer/descrambler. The proper operation of the byte multiplexer and demultiplexer has been verified in an OC-48 experiment with a bit error rate (BER) of less than 10/sup -14/. It is shown that the byte-interleaving architecture leads to a simple and modular implementation of higher-rate interfaces (such as OC-192 at 9.95 Gbit/s) using state-of-the-art technologies.>

The authors examine the physical design issues associated with terabit/second switching systems, particularly with regard to the customer access portion of the switch. They determine the physical design requirements in the areas of backplane interconnections, integrated circuit packaging, and circuit board technology and identify areas where existing- or near-future physical design technologies are inadequate to meet the requirements of this application. A new 3D interconnection architecture that solves some of the problems encountered at the backplane level is suggested. It is also suggested that multichip module technology will help meet some of the speed and density requirements at the chip packaging level. Some of the system-level consequences of the proposed model are discussed.>

The circuit switching fabric for broadband networks will demand numerous densely interconnected components, with channel rates as high as 150 Mbit/s, This is a natural application area for VLSI, which motivates the evaluation of the key technologies and requirements for realizable broadband circuit and packet switching systems. The critical circuit switching capabilities include the basic crosspoint array, I/O interface between circuit packs, jitter removal and regeneration, and multichannel phase alignment. This paper describes results obtained in these four critical areas. With remote multiplexing units, the greatest constraints are power dissipation and system volume. CMOS circuitry has the advantage here, because of its intrinsic usage-sensitive low power operation. The challenge is to prove that CMOS processes and designs are compatible with the high data and clock rates required of broadband ISDN systems. A fully connected 16 × 16 crosspoint array has been implemented by several laboratories. In this paper we will report on our asynchronous 16 × 16 switching chips fabricated in a 2 μm CMOS process. These devices support channel rates of up to 240 Mbit/s. Crosstalk, jitter accumulation, and power dissipation dominate system issues at the IC interface, making simple CMOS or TTL signaling inappropriate for broadband applications. We will discuss the ECL compatible signaling used in our broadband CMOS IC's. This low noise interface is currently operating at 150-200 MHz rates. We will stress the resulting improvement in noise and jitter accumulation. We will also consider a broader class of low power signaling schemes, including CMOS to GaAsFET direct interfacing. The physical design of switching fabric components will be at least as important as the electronics. Our custom high-density chip carrier and surface mounting arrangement will be discussed, which offers a fourfold reduction in parasitic inductance and capacitance, with corresponding reductions in crosstalk, jitter, and interconnect power dissipation. Pulses normally degrade after passing through asynchronous crosspoint elements. A scalable switching fabric must include regeneration to control this accumulated noise and jitter. We have demonstrated the critical components of such a regenerator, including VCO's, process independent digital phase shifters, phase error detectors, and data relocking circuitry. Existing CMOS technology can support the circuit switching requirements for broadband networks. A thorough understanding of the interface capabilities and requirements will be necessary to deliver functional hardware. The knowledge gained in this work will have direct application to packet switch constraints and performance.