The analysis and design of a new ΔΣ frequency discriminator (FD) architecture is presented in this paper. This architecture has finer frequency resolution and lower noise compared to existing architectures. This superior performance is achieved by incorporating a fractional-N divider and a multi-bit quantizer. This new architecture is based on ΔΣ modulation techniques and converts instantaneous frequency directly to digital form. System level simulation models were developed in Matlab Simulink to explore the effects of various parameters on performance. The architecture was then partitioned into circuit blocks. Each of the circuit blocks was simulated at both the behavioural and the transistor level. This FD architecture is suitable for high resolution frequency synthesis.

In this paper a novel architecture for a second order /spl Delta//spl Sigma/ frequency-to-digital converter (FDC), aimed at receive path applications, is presented. The new architecture uses fractional-N division techniques in order to reduce the fullscale input range and out of band quantization noise when used to detect small deviation FM signals, relative to the reference frequency. The output is a single bit bitstream whose average density is an accurate representation of the instantaneous frequency deviations of the modulated IF signal.

A new architecture is proposed for a synthesizer suitable for mobile radio applications. This architecture has several advantages over the fractional-N type architectures currently used. The new synthesizer is based on an oversampled /spl Sigma/-/spl Delta/ frequency discriminator in the feedback path which converts the frequency to digital form. This results in a largely digital architecture that eliminates many of the analog noise sources that plague conventional fractional-N synthesizers.

A new form of spread-spectrum transmission, interpolated frequency-hopping (IFH), uses a digital interpolation filter to reduce the high frequency content of the hopping code in a phase-locked loop (PLL) based frequency-hopping system, reducing the transient phase-error generated in the loop. Experimental results presented in this paper show that IFH reduces intermediate frequency (IF) distortion caused by PLL synthesizer mismatch in standard frequency-hopping systems, reducing the bit-error rate.

A novel realization of an adaptive filter using sampled analog MOS LSI techniques is described in this paper. The basic functional block of the adaptive filter is an electrically programmable transversal filter whose tap weights are modified according to the least mean square algorithm. A comparison has been made among different available approaches for implementing a programmable transversal filter. A rotating tap weight structure [1] has been used to realize a 32-tap programmable transversal filter with features for the adaptive operation included on an NMOS silicon-gate chip. The adaptive filter has been characterized as a parameter estimator which finds application in echo cancellation and noise cancellation. A wide range of magnitude and phase characteristics of the unknown system (to be modeled by the adaptive filter) have been used to test the performance of the present adaptive system. Results on the residual error and the convergence time under different conditions are reported. Some practical limitations of the system are also presented.