Demo Data from SIGIR 2026 / reviewers in the wild / expert
Javier Fresno
dblp:23/9378
· DBLP profile ↗
4ranked-venue papers
3as first author
0since 2021 · last 2014
0000-0002-2658-1101ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 2 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Parallel and multicore computing · 80% High-performance computing · 20% |
Topics — the 5 heaviest of 6, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Parallel and multicore computing
data distribution |
0.2 | 2 | 2014 | An Extensible System for Multilevel Automatic Data Partition and Mapping · IEEE Trans. Parallel Distributed Syst. 2014 Blending Extensibility and Performance in Dense and Sparse Parallel Data Management · IEEE Trans. Parallel Distributed Syst. 2014 |
Parallel and multicore computing
parallel libraries |
0.2 | 1 | 2014 | Blending Extensibility and Performance in Dense and Sparse Parallel Data Management · IEEE Trans. Parallel Distributed Syst. 2014 |
High-performance computing › sparse linear algebra
sparse matrix computation |
0.2 | 1 | 2014 | Blending Extensibility and Performance in Dense and Sparse Parallel Data Management · IEEE Trans. Parallel Distributed Syst. 2014 |
Parallel and multicore computing
parallel programming models |
0.1 | 1 | 2014 | Blending Extensibility and Performance in Dense and Sparse Parallel Data Management · IEEE Trans. Parallel Distributed Syst. 2014 |
Parallel and multicore computing
parallel programming runtimes |
0.1 | 1 | 2014 | An Extensible System for Multilevel Automatic Data Partition and Mapping · IEEE Trans. Parallel Distributed Syst. 2014 |
Methods — techniques the papers use, named apart from their topics
static and dynamic load balancing · 0.2parallel strategy · 0.2modular library design · 0.2hierarchical tiling · 0.2data representation decoupling · 0.2
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2014 | Blending Extensibility and Performance in Dense and Sparse Parallel Data ManagementabstractDealing with both dense and sparse data in parallel environments usually leads to two different approaches: To rely on a monolithic, hard-to-modify parallel library, or to code all data management details by hand. In this paper we propose a third approach, that delivers good performance while the underlying library structure remains modular and extensible. Our solution integrates dense and sparse data management using a common interface, that also decouples data representation, partitioning, and layout from the algorithmic and parallel strategy decisions of the programmer. Our experimental results in different parallel environments show that this new approach combines the flexibility obtained when the programmer handles all the details with a performance comparable to the use of a state-of-the-art, sparse matrix parallel library. Javier Fresno, Arturo González-Escribano, Diego R. Llanos Ferraris |
IEEE Trans. Parallel Distributed Syst. | 1 |
| 2014 | An Extensible System for Multilevel Automatic Data Partition and MappingabstractAutomatic data distribution is a key feature to obtain efficient implementations from abstract and portable parallel codes. We present a highly efficient and extensible runtime library that integrates techniques for automatic data partition and mapping. It uses a novel approach to define an abstract interface and a plug-in system to encapsulate different types of regular and irregular techniques, helping to generate codes which are independent of the exact mapping functions selected. Currently, it supports hierarchical tiling of arrays with dense and stride domains, that allows the implementation of both data and task parallelism using a SPMD model. It automatically computes appropriate domain partitions for a selected virtual topology, mapping them to available processors with static or dynamic load-balancing techniques. Our library also allows the construction of reusable communication patterns that efficiently exploit MPI communication capabilities. The use of our library greatly reduces the complexity of data distribution and communication, hiding the details of the underlying architecture. The library can be used as an abstract layer for building generic tiling operations as well. Our experimental results show that the use of this library allows to achieve similar performance as carefully-implemented manual versions for several, well-known parallel kernels and benchmarks in distributed and multicore systems, and substantially reduces programming effort. Arturo González-Escribano, Yuri Torres, Javier Fresno, Diego R. Llanos Ferraris |
IEEE Trans. Parallel Distributed Syst. | 3 |
| 2013 | Extending a hierarchical tiling arrays library to support sparse data partitioning
Javier Fresno, Arturo González-Escribano, Diego R. Llanos Ferraris |
J. Supercomput. | 1 |
| 2011 | Automatic Data Partitioning Applied to Multigrid PDE SolversabstractThis paper studies the impact of using automatic data-layout techniques on the process of coding the well-known multigrid MG NAS parallel benchmark. We describe the sequential problem in detail, and discuss the parallel version and its optimizations. Then, we implement the parallel algorithm using Hit map, a highly-efficient modular library for hierarchical tiling and mapping of arrays. We describe how to use the library plug-in system to add a new data-layout module that encapsulates a generalization of the data-alignment policy of the MG benchmark. The module system applies this policy to automatically adapt the data distribution and communication code to any grain level. The impact of using these techniques is qualitatively and quantitatively described in terms of development effort and performance. Our results show that it is possible to introduce flexible automatic data-layout techniques in current parallel compiler technology, without sacrificing performance. Javier Fresno, Arturo González-Escribano, Diego R. Llanos Ferraris |
PDP | 1 |