Dual-output look-up tables (LUTs) are supported by modern commercial Field-Programmable Gate Array (FPGA) architectures. Existing technology mapping usually generates multi-output LUTs by merging single-output LUTs. However, these mapping solutions often fail to fully leverage the multi-output capability. This paper proposes a novel FPGA mapping scheme for multi-output logic units, aiming to improve synthesis performance significantly. By introducing new metrics functions, k-input l-output cut (kl-cut) generation method, and methods to add secondary LUT outputs, the proposed approach enables thorough exploration of the design space. Results show that the proposed dual-output LUT synthesis method achieves 30.2% and 34.7% reduction in LUT usage and depth, respectively, outperforming leading-edge dual-output mapping tools. In addition, the proposed mapping scheme is applied to an emerging field-programmable unit, MCluster, proving compatibility and efficiency on non-LUT logic blocks. For the first time, we perform a system-level design flow to demonstrate the benefit of multi-output LUT at the system level and provide critical insights and design trade-offs.

Reconfigurable devices are gaining increasing attention as a viable alternative and supplementary solution to the traditional CMOS technology. In this article, we develop a more efficient field-programmable gate array (FPGA) based on the reconfigurable field-effective transistor (RFET). We use the multi-gate characteristics of RFET to redesign the key components of FPGAs, namely SRAM-controlled multiplexer and look-up tables. The compact structure of the proposed design requires fewer transistors and leads to reduced delay of the overall FPGA system. In addition, we develop a comprehensive technology/system co-design and co-optimization framework to thoroughly investigate the design space, including various device- and system-level design parameters. A series of benchmark tests show that under the optimal design, up to 32% and 13% reduction can be achieved in delay and energy-delay product (EDP), respectively, compared to the traditional CMOS FPGAs.

A recent surge of research on deep convolutional neural network (DCNN) has given a challenge on existing computation architecture which has the flows in speed and memory bottleneck. In the pretreatment of deep learning, mask operation is frequently used to remove noise or fetch information. However, under data-intensive conditions, applying mask frequently can put an extremely heavy memory/communication burden on computing system. An efficient substrate of DCNN for ameliorating mask operation is urgently needed. In this paper, we present a self-renewing mask circuit (SRMC) to alleviate/solve earlier problems. First, a new approach to apply mask is presented based on computation-in-memory architecture that implements high-performance processor and high-density memory in the same physical location. Second, we designed the peripheral circuit which can provide self-renewing function to further avoid the data exchange with an external space. As opposed to most other computational element, which calculates two 1-bit data, the proposed SRMC storage multibit value and calculate several of them parallel. The calculating ability of SRMC is significantly superior to those of computational element in general architectures. Moreover, mean filter and edge detector are implemented to illustrate the effectiveness and scalability of the proposed circuit. Finally, we discussed two possible methods to enhance the practicability of our scheme.