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David Kuang-Hui Yu

dblp:233/2793 · DBLP profile ↗
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3ranked-venue papers
3as first author
1since 2021 · last 2022
0000-0002-6841-9866ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 first-author · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Storage systems · 100%

Topics — the 8 heaviest of 8, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Storage systems › flash and SSD
flash memory
0.612022
Differential Evolution Algorithm With Asymmetric Coding for Solving the Reliability Problem of 3D-TLC CT Flash-Memory Storage Systems · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2022
Storage systems › flash and SSD
flash memory reliability
0.612022
Differential Evolution Algorithm With Asymmetric Coding for Solving the Reliability Problem of 3D-TLC CT Flash-Memory Storage Systems · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2022
Storage systems
flash and SSD
0.412020
A Management Scheme of Multi-Level Retention-Time Queues for Improving the Endurance of Flash-Memory Storage Devices · IEEE Trans. Computers 2020
Storage systems › storage reliability › durability
flash lifetime
0.412020
A Management Scheme of Multi-Level Retention-Time Queues for Improving the Endurance of Flash-Memory Storage Devices · IEEE Trans. Computers 2020
Storage systems › flash and SSD › flash memory management
wear leveling
0.412020
A Management Scheme of Multi-Level Retention-Time Queues for Improving the Endurance of Flash-Memory Storage Devices · IEEE Trans. Computers 2020
Storage systems › flash and SSD
solid-state drive
0.212022
Differential Evolution Algorithm With Asymmetric Coding for Solving the Reliability Problem of 3D-TLC CT Flash-Memory Storage Systems · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2022
Storage systems › storage reliability › durability
data retention
0.112020
A Management Scheme of Multi-Level Retention-Time Queues for Improving the Endurance of Flash-Memory Storage Devices · IEEE Trans. Computers 2020
Storage systems
storage reliability
0.112020
A Management Scheme of Multi-Level Retention-Time Queues for Improving the Endurance of Flash-Memory Storage Devices · IEEE Trans. Computers 2020

Methods — techniques the papers use, named apart from their topics

differential evolution · 0.6asymmetric coding · 0.6refreshment scheme · 0.4multi-level retention-time queues · 0.4garbage collection · 0.4
YearPublicationVenuePosition
2022 Differential Evolution Algorithm With Asymmetric Coding for Solving the Reliability Problem of 3D-TLC CT Flash-Memory Storage Systems
abstract
In recent years, NAND flash memory has been widely used in mobile devices, laptops, desktops, and data center storage systems due to its low-power consumption, high performance, high density, lightweight, shock resistance, and high-reliability natures. However, as the stacked layers and the storage density increase, flash memory also suffers from a higher raw bit error rate (RBER) and shorter lifetime. Observing that reliable cell states suffer from less data retention errors and program disturbance, we propose a differential evolution coding scheme to increase the probability of storing data in more reliable cell states, thereby reducing the RBER. We conducted the experiments over a development platform of SSD storage device with 3D-TLC charge trap (CT) NAND flash memory. The experimental results showed that the proposed differential evolution algorithm with asymmetric coding scheme could averagely reduce RBER by 48.88%, 65.45%, 52.61%, 61.99%, 80.19%, and 33.18% compared with baseline, asymmetric coding algorithm, asymmetric coding scheme with stripe-pattern elimination algorithm, UAC-$n$LC, word-line batch score modulation programming, and SCB schemes.
David Kuang-Hui Yu, Jen-Wei Hsieh
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1
2020 A Management Scheme of Multi-Level Retention-Time Queues for Improving the Endurance of Flash-Memory Storage Devices
abstract
As flash memory technology has been scaled down to 1x nm and more bits can be stored in a cell, the storage density of flash memory has been significantly improved. However, these technical trends also severely hurt the programming speed and endurance of flash memory. The internal data retention time is the duration for which a flash cell can correctly hold data. By relaxing internal data retention time, both the page programming speed and the block endurance could be improved. However, the retention time of flash memory typically requires to last for several years according to the industrial standard. Thus a refreshment scheme is required to deal with the decreasing of retention time. In this article, we propose multi-level retention-time queues with a management scheme to meet the retention-time requirement for a reliable storage system. Observing that many data are overwritten in hours or days in real workloads, multiple retention-time queues could effectively separate data with different update frequencies. There are three challenge issues for a proper design: (1) Since access pattern might change from time to time, a technical issue is how to promote/demote data so that data could be maintained in the proper retention-time queue to minimize the refreshment overhead. (2) Another technical issue is how to refresh each retention-time queue in time to guarantee data integrity. (3) Since blocks resided in different retention-time queue would suffer from different level of wearing, the third technical issue is how to estimate wearing status of flash-memory blocks in an effective and efficient manner to achieve wear leveling. In our scheme, data allocator, multi-level refresh module, garbage collector, and wear leveler are introduced to deal with these technical issues. Based on our experimental results, not only endurance and performance but also energy consumption of the flash-memory storage system could be significantly improved by our scheme.
David Kuang-Hui Yu, Jen-Wei Hsieh
IEEE Trans. Computers1
2018 Retention-Time Relaxation Scheme for MLC Flash-Memory Storage Systems
abstract
As flash memory technology has been scaled to 1xnm and more bits can be stored in a cell, the storage density of flash memory has been significantly improved. However, these technical trends also severely hurt the programming speed and endurance of flash memory. The internal data retention time is the duration for which a flash cell can correctly hold data. By relaxing internal data retention time, both the page programming speed and the block endurance could be improved. However, the retention time of flash memory typically requires to last for several years according to the industrial standard. Thus a refreshment scheme is required to deal with the decreasing of retention time. In this paper, we present a retention-time relaxation scheme to meet the retention-time requirement for a reliable storage system. Observing that many data are overwritten in hours or days in real workloads, multiple retention-time queues are maintained to store data with different update frequency separately. Since access pattern might change from time to time, one technical issue is how to promote/demote data so that data could be maintained in the proper retention-time queue to minimize the refreshment overhead. Another technical issue is how to efficiently and effectively refresh each retention-time queue in time to guarantee data integrity. In our scheme, data allocator and multi-level refresh module are proposed to deal with these technical issues. Based on the experimental results, not only endurance and performance but also energy consumption of the flash-memory storage system could be significantly improved by our scheme.
David Kuang-Hui Yu, Jen-Wei Hsieh
RTCSA1