Demo Data from SIGIR 2026 / reviewers in the wild / expert
Simon Cooksey
dblp:234/6115
· DBLP profile ↗
5ranked-venue papers
0as first author
4since 2021 · last 2025
0000-0001-9365-9717ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Software engineering, systems software and programming languages · 5 · 4 since 2021Systems, architecture and hardware · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Software engineering, system software, and programming languages
2 papers |
Concurrent programming · 65% Program verification · 26% Program analysis · 6% | |
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
GPUs and heterogeneous computing · 61% Memory systems · 30% Hardware accelerators and domain-specific architectures · 9% |
Topics — the 11 heaviest of 11, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Concurrent programming
memory models |
1.4 | 2 | 2025 | Symbolic MRD: Dynamic Memory, Undefined Behaviour, and Extrinsic Choice · Proc. ACM Program. Lang. 2025 The leaky semicolon: compositional semantic dependencies for relaxed-memory concurrency · Proc. ACM Program. Lang. 2022 |
Concurrent programming › memory models › weak memory models
c11 memory model |
0.9 | 1 | 2025 | Symbolic MRD: Dynamic Memory, Undefined Behaviour, and Extrinsic Choice · Proc. ACM Program. Lang. 2025 |
Program verification
predicate transformers |
0.6 | 1 | 2022 | The leaky semicolon: compositional semantic dependencies for relaxed-memory concurrency · Proc. ACM Program. Lang. 2022 |
Program verification
program logic |
0.6 | 1 | 2022 | The leaky semicolon: compositional semantic dependencies for relaxed-memory concurrency · Proc. ACM Program. Lang. 2022 |
Concurrent programming › memory models
weak memory models |
0.6 | 1 | 2022 | The leaky semicolon: compositional semantic dependencies for relaxed-memory concurrency · Proc. ACM Program. Lang. 2022 |
GPUs and heterogeneous computing › GPU memory
GPU memory consistency |
0.6 | 1 | 2022 | Mixed-proxy extensions for the NVIDIA PTX memory consistency model: industrial product · ISCA 2022 |
GPUs and heterogeneous computing › GPU memory
GPU memory model |
0.6 | 1 | 2022 | Mixed-proxy extensions for the NVIDIA PTX memory consistency model: industrial product · ISCA 2022 |
Memory systems › memory consistency
memory consistency model |
0.6 | 1 | 2022 | Mixed-proxy extensions for the NVIDIA PTX memory consistency model: industrial product · ISCA 2022 |
Program analysis › static analysis
pointer analysis |
0.3 | 1 | 2025 | Symbolic MRD: Dynamic Memory, Undefined Behaviour, and Extrinsic Choice · Proc. ACM Program. Lang. 2025 |
Compilers and program optimization › instruction scheduling
instruction reordering |
0.2 | 1 | 2022 | The leaky semicolon: compositional semantic dependencies for relaxed-memory concurrency · Proc. ACM Program. Lang. 2022 |
Hardware accelerators and domain-specific architectures
tensor accelerator |
0.2 | 1 | 2022 | Mixed-proxy extensions for the NVIDIA PTX memory consistency model: industrial product · ISCA 2022 |
Methods — techniques the papers use, named apart from their topics
operational semantics · 0.9executable semantics · 0.9preconditions · 0.6event-based semantics · 0.6
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | Symbolic MRD: Dynamic Memory, Undefined Behaviour, and Extrinsic ChoiceabstractWe present the first thin-air free memory model that admits compiler optimisations that aggressively leverage knowledge from alias analysis, an assumption of freedom from undefined behaviour, and from the extrinsic choices of real implementations such as over-alignment. Our model has tooling support with state-of-the-art performance, executing a battery of tests orders of magnitude quicker than other executable thin-air free semantics. The model integrates with the C/C++ memory model through an exportable semantic dependency relation, it allows standard compilation mappings for atomics, and it matches all tests in the recently published desiderata for C/C++ from the ISO. Jay Richards, Daniel Wright 0001, Simon Cooksey, Mark Batty |
Proc. ACM Program. Lang. | 3 |
| 2023 | Rust for Morello: Always-On Memory Safety, Even in Unsafe Code (Experience Paper)abstractMemory safety issues are a serious concern in systems programming. Rust is a systems language that provides memory safety through a combination of a static checks embodied in the type system and ad hoc dynamic checks inserted where this analysis becomes impractical. The Morello prototype architecture from ARM uses capabilities, fat pointers augmented with object bounds information, to catch failures of memory safety. This paper presents a compiler from Rust to the Morello architecture, together with a comparison of the performance of Rust’s runtime safety checks and the hardware-supported checks of Morello. The cost of Morello’s always-on memory safety guarantees is 39% in our 19 benchmark suites from the Rust crates repository (comprising 870 total benchmarks). For this cost, Morello’s capabilities ensure that even unsafe Rust code benefits from memory safety guarantees. Sarah Harris, Simon Cooksey, Michael Vollmer 0003, Mark Batty |
ECOOP | 2 |
| 2022 | Mixed-proxy extensions for the NVIDIA PTX memory consistency model: industrial productabstractIn recent years, there has been a trend towards the use of accelerators and architectural specialization to continue scaling performance in spite of a slowing of Moore's Law. GPUs have always relied on dedicated hardware for graphics workloads, but modern GPUs now also incorporate compute-domain accelerators such as NVIDIA's Tensor Cores for machine learning. For these accelerators to be successfully integrated into a general-purpose programming language such as C++ or CUDA, there must be a forward- and backward-compatible API for the functionality they provide. To the extent that all of these accelerators interact with program threads through memory, they should be incorporated into the GPU's memory consistency model. Unfortunately, the use of accelerators and/or special non-coherent paths into memory produces non-standard memory behavior that existing GPU memory models cannot capture. Daniel Lustig, Simon Cooksey, Olivier Giroux |
ISCA | 2 |
| 2022 | The leaky semicolon: compositional semantic dependencies for relaxed-memory concurrencyabstractProgram logics and semantics tell a pleasant story about sequential composition: when executing (S1;S2), we first execute S1 then S2. To improve performance, however, processors execute instructions out of order, and compilers reorder programs even more dramatically. By design, single-threaded systems cannot observe these reorderings; however, multiple-threaded systems can, making the story considerably less pleasant. A formal attempt to understand the resulting mess is known as a “relaxed memory model.” Prior models either fail to address sequential composition directly, or overly restrict processors and compilers, or permit nonsense thin-air behaviors which are unobservable in practice. To support sequential composition while targeting modern hardware, we enrich the standard event-based approach with preconditions and families of predicate transformers. When calculating the meaning of (S1; S2), the predicate transformer applied to the precondition of an event e from S2 is chosen based on the set of events in S1 upon which e depends. We apply this approach to two existing memory models. Alan Jeffrey, James Riely, Mark Batty, Simon Cooksey, Ilya Kaysin, Anton Podkopaev |
Proc. ACM Program. Lang. | 4 |
| 2020 | Modular Relaxed Dependencies in Weak Memory ConcurrencyabstractAbstract We present a denotational semantics for weak memory concurrency that avoids thin-air reads, provides data-race free programs with sequentially consistent semantics (DRF-SC), and supports a compositional refinement relation for validating optimisations. Our semantics identifies false program dependencies that might be removed by compiler optimisation, and leaves in place just the dependencies necessary to rule out thin-air reads. We show that our dependency calculation can be used to rule out thin-air reads in any axiomatic concurrency model, in particular C++. We present a tool that automatically evaluates litmus tests, show that we can augment C++ to fix the thin-air problem, and we prove that our augmentation is compatible with the previously used compilation mappings over key processor architectures. We argue that our dependency calculation offers a practical route to fixing the longstanding problem of thin-air reads in the C++ specification. Marco Paviotti, Simon Cooksey, Anouk Paradis, Daniel Wright 0001, Scott Owens, Mark Batty |
ESOP | 2 |