Demo Data from SIGIR 2026 / reviewers in the wild / expert
Anthony Demeri
dblp:235/4730
· DBLP profile ↗
2ranked-venue papers
1as first author
0since 2021 · last 2020
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Software engineering, systems software and programming languages · 2 · 1 first-authorSystems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Memory systems · 44% Storage systems · 35% Distributed systems · 22% |
Topics — the 6 heaviest of 6, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Storage systems
crash consistency |
0.4 | 1 | 2020 | Durable Transactional Memory Can Scale with Timestone · ASPLOS 2020 |
Distributed systems › concurrency control
multi-version concurrency control |
0.4 | 1 | 2020 | Durable Transactional Memory Can Scale with Timestone · ASPLOS 2020 |
Memory systems › non-volatile memory
non-volatile main memory |
0.4 | 1 | 2020 | Durable Transactional Memory Can Scale with Timestone · ASPLOS 2020 |
Memory systems › non-volatile memory › persistent memory
persistent transactional memory |
0.4 | 1 | 2020 | Durable Transactional Memory Can Scale with Timestone · ASPLOS 2020 |
Storage systems
logging |
0.1 | 1 | 2020 | Durable Transactional Memory Can Scale with Timestone · ASPLOS 2020 |
Storage systems › flash and SSD › flash memory management › garbage collection
write amplification |
0.1 | 1 | 2020 | Durable Transactional Memory Can Scale with Timestone · ASPLOS 2020 |
Methods — techniques the papers use, named apart from their topics
multi-version concurrency control · 0.4hybrid logging · 0.4
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2020 | Durable Transactional Memory Can Scale with TimestoneabstractNon-volatile main memory (NVMM) technologies promise byte addressability and near-DRAM access that allows developers to build persistent applications with common load and store instructions. However, it is difficult to realize these promises because NVMM software should also provide crash consistency while providing high performance, and scalability. Durable transactional memory (DTM) systems address these challenges. However, none of them scale beyond 16 cores. The poor scalability either stems from the underlying STM layer or from employing limited write parallelism (single writer or dual version). In addition, other fundamental issues with guaranteeing crash consistency are high write amplification and memory footprint in existing approaches. To address these challenges, we propose TimeStone: a highly scalable DTM system with low write amplification and minimal memory footprint. TimeStone uses a novel multi-layered hybrid logging technique, called TOC logging, to guarantee crash consistency. Also, TimeStone further relies on Multi-Version Concurrency Control (MVCC) mechanism to achieve high scalability and to support different isolation levels on the same data set. Our evaluation of TimeStone against the state-of-the-art DTM systems shows that it significantly outperforms other systems for a wide range of workloads with varying data-set size and contention levels, up to 112 hardware threads. In addition, with our TOC logging, TimeStone achieves a write amplification of less than 1, while existing DTM systems suffer from 2×-6× overhead. Madhava Krishnan Ramanathan, Ajit Mathew, Xinwei Fu, Anthony Demeri, Changwoo Min, Sudarsun Kannan |
ASPLOS | 5 |
| 2020 | Poseidon: Safe, Fast and Scalable Persistent Memory AllocatorabstractPersistent memory allocator is an essential component of any Non-Volatile Main Memory (NVMM) application. A slow memory allocator can bottleneck the entire application stack, while an unsecure memory allocator can render applications inconsistent upon program bugs or system failure. Unlike DRAM-based memory allocators, it is indispensable for an NVMM allocator to guarantee its heap metadata safety from both internal and external errors. An effective NVMM memory allocator should be 1) safe, 2) scalable, and 3) high performing. Unfortunately, none of the existing persistent memory allocators achieve all three requisites. For example, we found that even Intel's de-facto NVMM allocator-libpmemobj is vulnerable to silent data corruption and persistent memory leaks resulting from a simple heap overflow. Anthony Demeri, Wook-Hee Kim, Madhava Krishnan Ramanathan, Mohannad Ismail, Changwoo Min |
Middleware | 1 |