Demo Data from SIGIR 2026 / reviewers in the wild / expert
Midhul Vuppalapati
dblp:237/0851
· DBLP profile ↗
11ranked-venue papers
5as first author
8since 2021 · last 2026
0000-0002-6659-1224ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Computer networks · 4 · 2 first-author · 3 since 2021Software engineering, systems software and programming languages · 4 · 3 first-author · 4 since 2021Systems, architecture and hardware · 3 · 1 since 2021Databases, data management, data science and information retrieval · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
11 papers |
Memory systems · 40% Cloud and datacenter computing · 23% Storage systems · 16% | |
| Computer networks
3 papers |
Datacenter networks · 100% | |
| Software engineering, system software, and programming languages
3 papers |
Operating systems · 100% | |
| Network and information security
1 paper |
Cryptographic protocols and secure computation · 100% |
Topics — the 24 heaviest of 28, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Performance modeling and evaluation
workload characterization |
1.5 | 3 | 2024 | Understanding the Host Network · SIGCOMM 2024 Understanding host network stack overheads · SIGCOMM 2021 Tiered Memory Management: Access Latency is the Key! · SOSP 2024 |
Operating systems
network stack |
1.1 | 2 | 2022 | Towards μs tail latency and terabit ethernet: disaggregating the host network stack · SIGCOMM 2022 Understanding host network stack overheads · SIGCOMM 2021 |
Memory systems
memory disaggregation |
1.0 | 1 | 2026 | CXL in Cloud Practice: Practical Lessons for Incrementally Scaling Deployment · IEEE Trans. Computers 2026 |
Memory systems
memory expansion |
1.0 | 1 | 2026 | CXL in Cloud Practice: Practical Lessons for Incrementally Scaling Deployment · IEEE Trans. Computers 2026 |
Storage systems › file systems
cluster file systems |
0.8 | 2 | 2020 | INSTalytics: Cluster Filesystem Co-design for Big-data Analytics · ACM Trans. Storage 2020 INSTalytics: Cluster Filesystem Co-design for Big-data Analytics · FAST 2019 |
Cloud and datacenter computing
datacenter application performance |
0.8 | 1 | 2024 | Understanding the Host Network · SIGCOMM 2024 |
Memory systems
memory access latency |
0.8 | 1 | 2024 | Tiered Memory Management: Access Latency is the Key! · SOSP 2024 |
Memory systems
page placement |
0.8 | 1 | 2024 | Tiered Memory Management: Access Latency is the Key! · SOSP 2024 |
Memory systems › tiered memory
tiered memory management |
0.8 | 1 | 2024 | Tiered Memory Management: Access Latency is the Key! · SOSP 2024 |
Cloud and datacenter computing
cluster resource management and scheduling |
0.7 | 1 | 2023 | Karma: Resource Allocation for Dynamic Demands · OSDI 2023 |
Cloud and datacenter computing
resource allocation |
0.7 | 1 | 2023 | Karma: Resource Allocation for Dynamic Demands · OSDI 2023 |
Datacenter networks
datacenter transport |
0.6 | 1 | 2022 | Towards μs tail latency and terabit ethernet: disaggregating the host network stack · SIGCOMM 2022 |
Datacenter networks › low-latency networking
tail latency reduction |
0.6 | 1 | 2022 | Towards μs tail latency and terabit ethernet: disaggregating the host network stack · SIGCOMM 2022 |
Distributed systems
fault tolerance |
0.6 | 1 | 2022 | SHORTSTACK: Distributed, Fault-tolerant, Oblivious Data Access · OSDI 2022 |
Memory systems
oblivious memory access |
0.6 | 1 | 2022 | SHORTSTACK: Distributed, Fault-tolerant, Oblivious Data Access · OSDI 2022 |
Cloud and datacenter computing
big data analytics |
0.5 | 2 | 2020 | INSTalytics: Cluster Filesystem Co-design for Big-data Analytics · FAST 2019 INSTalytics: Cluster Filesystem Co-design for Big-data Analytics · ACM Trans. Storage 2020 |
Storage systems › i/o architecture › i/o subsystem
i/o stack |
0.5 | 1 | 2021 | Rearchitecting Linux Storage Stack for µs Latency and High Throughput · OSDI 2021 |
Storage systems › storage performance
low-latency storage |
0.5 | 1 | 2021 | Rearchitecting Linux Storage Stack for µs Latency and High Throughput · OSDI 2021 |
Distributed and cloud data management › distributed database architecture
disaggregated storage |
0.4 | 1 | 2020 | Building An Elastic Query Engine on Disaggregated Storage · NSDI 2020 |
Parallel and multicore computing
data distribution |
0.4 | 1 | 2020 | INSTalytics: Cluster Filesystem Co-design for Big-data Analytics · ACM Trans. Storage 2020 |
Memory systems
memory interconnect |
0.2 | 1 | 2024 | Understanding the Host Network · SIGCOMM 2024 |
Hardware accelerators and domain-specific architectures
network accelerator |
0.2 | 1 | 2022 | Towards μs tail latency and terabit ethernet: disaggregating the host network stack · SIGCOMM 2022 |
Operating systems › i/o › i/o subsystem
i/o scheduling |
0.1 | 1 | 2021 | Rearchitecting Linux Storage Stack for µs Latency and High Throughput · OSDI 2021 |
Storage systems › distributed storage
disaggregated storage |
0.1 | 1 | 2020 | Building An Elastic Query Engine on Disaggregated Storage · NSDI 2020 |
Methods — techniques the papers use, named apart from their topics
packet processing pipelines · 1.7disaggregation · 1.7production datacenter measurement · 1.5userspace networking · 1.5kernel optimization · 1.5hardware offload · 1.5error rate analysis · 1.0end-to-end latency decomposition · 1.0page migration · 0.8access tracking · 0.8
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2026 | CXL in Cloud Practice: Practical Lessons for Incrementally Scaling DeploymentabstractThis paper explores learnings from first-generation Compute Express Link (CXL) memory expansion to accelerate CXL’s journey to broad, robust use. While broad adoption will be a long journey similar to that of RDMA, we argue that the first step—CXL.mem expansion—is viable on today’s hardware. Through an end-to-end analysis, we revisit common showstoppers: we decompose memory access latency and show that CPU and DRAM internals, rather than the CXL protocol, dominate latency and variability, and we demonstrate how system slack absorbs link error rates above nominal specifications. Along the way, we distill practical guidance on device validation, monitoring, failure modes, security, and multi-tenant interference, and we outline a pragmatic adoption pathway: solidify robust expansion first, prototype micro-pooling next, and move to selective sharing as the ecosystem matures. Daniel S. Berger, Karthik Kumar, Midhul Vuppalapati, Chet Douglas, Jesse Sathre, Ian Robinson, Mark D. Hill |
IEEE Trans. Computers | 3 |
| 2024 | Understanding the Host NetworkabstractThe host network integrates processor, memory, and peripheral interconnects to enable data transfer within the host. Several recent studies from production datacenters show that contention within the host network can have significant impact on end-to-end application performance. The goal of this paper is to build an in-depth understanding of such contention within the host network. Midhul Vuppalapati, Saksham Agarwal, Henry Schuh, Baris Kasikci, Arvind Krishnamurthy, Rachit Agarwal 0001 |
SIGCOMM | 1 |
| 2024 | Tiered Memory Management: Access Latency is the Key!abstractThe emergence of tiered memory architectures has led to a renewed interest in memory management. Recent works on tiered memory management innovate on mechanisms for access tracking, page migration, and dynamic page size determination; however, they all use the same page placement algorithm---packing the hottest pages in the default tier (one with the lowest hardware-specified memory access latency). This makes an implicit assumption that, despite serving the hottest pages, the access latency of the default tier is less than that of alternate tiers. This assumption is far from real: it is well-known in the computer architecture community that, in the realistic case of multiple in-flight requests, memory access latency can be significantly larger than the hardware-specified latency. We show that, even under moderate loads, the default tier access latency can inflate to be 2.5× larger than the latency of alternate tiers; and that, under this regime, performance of state-of-the-art memory tiering systems can be 2.3× worse than the optimal. Midhul Vuppalapati, Rachit Agarwal 0001 |
SOSP | 1 |
| 2023 | Karma: Resource Allocation for Dynamic Demands
Midhul Vuppalapati, Giannis Fikioris, Rachit Agarwal 0001, Asaf Cidon, Anurag Khandelwal, Éva Tardos |
OSDI | 1 |
| 2022 | SHORTSTACK: Distributed, Fault-tolerant, Oblivious Data Access
Midhul Vuppalapati, Kushal Babel, Anurag Khandelwal, Rachit Agarwal 0001 |
OSDI | 1 |
| 2022 | Towards μs tail latency and terabit ethernet: disaggregating the host network stackabstractDedicated, tightly integrated, and static packet processing pipelines in today's most widely deployed network stacks preclude them from fully exploiting capabilities of modern hardware. Qizhe Cai, Midhul Vuppalapati, Jae-Hyun Hwang, Christoforos E. Kozyrakis, Rachit Agarwal 0001 |
SIGCOMM | 2 |
| 2021 | Rearchitecting Linux Storage Stack for µs Latency and High Throughput
Jae-Hyun Hwang, Midhul Vuppalapati, Simon Peter 0001, Rachit Agarwal 0001 |
OSDI | 2 |
| 2021 | Understanding host network stack overheadsabstractTraditional end-host network stacks are struggling to keep up with rapidly increasing datacenter access link bandwidths due to their unsustainable CPU overheads. Motivated by this, our community is exploring a multitude of solutions for future network stacks: from Linux kernel optimizations to partial hardware offload to clean-slate userspace stacks to specialized host network hardware. The design space explored by these solutions would benefit from a detailed understanding of CPU inefficiencies in existing network stacks. Qizhe Cai, Shubham Chaudhary 0004, Midhul Vuppalapati, Jae-Hyun Hwang, Rachit Agarwal 0001 |
SIGCOMM | 3 |
| 2020 | Building An Elastic Query Engine on Disaggregated Storage
Midhul Vuppalapati, Justin Miron, Rachit Agarwal 0001, Dan Truong, Ashish Motivala, Thierry Cruanes |
NSDI | 1 |
| 2020 | INSTalytics: Cluster Filesystem Co-design for Big-data AnalyticsabstractWe present the design, implementation, and evaluation of INSTalytics , a co-designed stack of a cluster file system and the compute layer, for efficient big-data analytics in large-scale data centers. INSTalytics amplifies the well-known benefits of data partitioning in analytics systems; instead of traditional partitioning on one dimension, INSTalytics enables data to be simultaneously partitioned on four different dimensions at the same storage cost, enabling a larger fraction of queries to benefit from partition filtering and joins without network shuffle. To achieve this, INSTalytics uses compute-awareness to customize the three-way replication that the cluster file system employs for availability. A new heterogeneous replication layout enables INSTalytics to preserve the same recovery cost and availability as traditional replication. INSTalytics also uses compute-awareness to expose a new sliced-read API that improves performance of joins by enabling multiple compute nodes to read slices of a data block efficiently via co-ordinated request scheduling and selective caching at the storage nodes. We have built a prototype implementation of INSTalytics in a production analytics stack, and we show that recovery performance and availability is similar to physical replication, while providing significant improvements in query performance, suggesting a new approach to designing cloud-scale big-data analytics systems. Muthian Sivathanu, Midhul Vuppalapati, Bhargav S. Gulavani, Kaushik Rajan, Jyoti Leeka, Jayashree Mohan, Piyus Kedia |
ACM Trans. Storage | 2 |
| 2019 | INSTalytics: Cluster Filesystem Co-design for Big-data Analytics
Muthian Sivathanu, Midhul Vuppalapati, Bhargav S. Gulavani, Kaushik Rajan, Jyoti Leeka, Jayashree Mohan, Piyus Kedia |
FAST | 2 |