Demo Data from SIGIR 2026 / reviewers in the wild / expert
Tung-Wei Lin
dblp:238/8029
· DBLP profile ↗
4ranked-venue papers
2as first author
2since 2021 · last 2025
0000-0003-2352-2867ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 1 first-author · 1 since 2021Computer networks · 1 · 1 first-author · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Electronic design automation · 34% Energy-efficient computing · 34% Reconfigurable computing and FPGAs · 17% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Energy-efficient computing › dynamic power reduction
clock power reduction |
0.9 | 1 | 2025 | Graceful Register Clustering and Rebanking for Power and Timing Balancing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2025 |
Electronic design automation
physical design |
0.9 | 1 | 2025 | Graceful Register Clustering and Rebanking for Power and Timing Balancing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2025 |
Reconfigurable computing and FPGAs
multi-FPGA system |
0.4 | 1 | 2020 | Routing Topology and Time-Division Multiplexing Co-Optimization for Multi-FPGA Systems · DAC 2020 |
Integrated circuit design
low-power circuit design |
0.3 | 1 | 2025 | Graceful Register Clustering and Rebanking for Power and Timing Balancing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2025 |
Cloud and datacenter computing › resource management › resource multiplexing
time-division multiplexing |
0.1 | 1 | 2020 | Routing Topology and Time-Division Multiplexing Co-Optimization for Multi-FPGA Systems · DAC 2020 |
Methods — techniques the papers use, named apart from their topics
rebanking · 0.9mean shift clustering · 0.9lagrangian relaxation · 0.4column generation · 0.4
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | Model Residuals as Shields: A Two-Level Formulation to Defend Smart Grids From Poisoning AttacksabstractThe advancement of smart grids presents both vast opportunities and heightened cybersecurity risks. Data-driven defense mechanisms, though designed as a shield against these threats, can fall prey to poisoning attacks. We delve into regression settings, underscoring the imperative to fortify defenses against a spectrum of poison ratios, notably those above 0.5—an issue scarcely addressed in prior studies. Recognizing the susceptibilities of smart grids and their manipulable sensors, we exploit the very intent of poisoning attacks, compromising model accuracy, as our defense mechanism. Our proposed two-level optimization framework discerns between poisoned and authentic data based on model residuals, outperforming or matching existing methods in 72% to 77% of precision and 75% to 80% of recalls across various poisoning attacks, poison ratios, and datasets. Once the authentic data are identified, the trained model is adaptable for a variety of applications. Comprehensive evaluations on different smart grid datasets, pitted against myriad poisoning schemes, validate our methodology’s edge over existing methods. We also shed light on the implications of model misspecification originating from temporal auto-correlation, a common feature in IoT and smart grid data. Tung-Wei Lin, Padmaksha Roy, Yi Zeng 0005, Ming Jin 0002, Ruoxi Jia 0001, Chen-Ching Liu, Alberto L. Sangiovanni-Vincentelli |
IEEE Internet Things J. | 1 |
| 2025 | Graceful Register Clustering and Rebanking for Power and Timing BalancingabstractAs dynamic power has become the bottleneck to achieving low power, clock power reduction is crucial in modern IC design. Register clustering can effectively save clock power because of significantly reducing the number of clock sinks and register pin capacitance, clock routed wirelength, and the number of clock buffers. In this article, we propose effective mean shift to naturally form clusters according to register distribution without placement disruption. Effective mean shift fulfills the requirements to be a good register clustering algorithm because it needs no prespecified number of clusters, is insensitive to initializations, is robust to outliers, is tolerant of various register distributions, is efficient and scalable, and balances clock power reduction against timing degradation. Furthermore, we devise a rebanking mechanism to legalize the clustering result according to the adopted multibit register library. Experimental results show that our approach achieves superior power and timing balancing. Tung-Wei Lin, Ya-Chu Chang, Hao-Yu Wu, Iris Hui-Ru Jiang |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 2 |
| 2020 | Routing Topology and Time-Division Multiplexing Co-Optimization for Multi-FPGA SystemsabstractTime-division multiplexing (TDM) is widely used to overcome bandwidth limitations and thus enhances routability in multi-FPGA systems due to the shortage of I/O pins in an FPGA. However, multiplexed signals induce significant delays. To evaluate timing degradation, nets with similar criticalities are often grouped to form NetGroups. In this paper, we propose a framework concerning routing topology and time-division multiplexing co-optimization for multi-FPGA systems. The proposed framework first generates high-quality topologies considering Net-Group criticalities. Then, inspired by column generation, TDM ratio assignment is solved optimally by Lagrangian relaxation. Experimental results show that our approach outperforms the top three entries of ICCAD 2019 CAD Contest. Moreover, our TDM ratio assignment algorithm can further improve the results of the top three winners to almost as good as ours. Tung-Wei Lin, Wei-Chen Tai, Iris Hui-Ru Jiang |
DAC | 1 |
| 2019 | Graceful Register Clustering by Effective Mean Shift Algorithm for Power and Timing BalancingabstractAs the wide adoption of FinFET technology in mass production, dynamic power becomes the bottleneck to achieving low power. Therefore, clock power reduction is crucial in modern IC design. Register clustering can effectively save clock power because of significantly reducing the number of clock sinks and register pin capacitance, clock routed wirelength, and the number of clock buffers. In this paper, we propose effective mean shift to naturally form clusters according to register distribution without placement disruption. Effective mean shift fulfills the requirements to be a good register clustering algorithm because it needs no prespecified number of clusters, is insensitive to initializations, is robust to outliers, is tolerant of various register distributions, is efficient and scalable, and balances clock power reduction against timing degradation. Experimental results show that our approach outperforms state-of-the-art work on power and timing balancing, as well as efficiency and scalability. Ya-Chu Chang, Tung-Wei Lin, Iris Hui-Ru Jiang, Gi-Joon Nam |
ISPD | 2 |