Demo Data from SIGIR 2026 / reviewers in the wild / expert
Stella Lau
dblp:244/8329
· DBLP profile ↗
5ranked-venue papers
2as first author
4since 2021 · last 2024
0000-0003-3921-9440ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Software engineering, systems software and programming languages · 4 · 1 first-author · 3 since 2021Systems, architecture and hardware · 2 · 2 since 2021Security and privacy · 1 · 1 first-author · 1 since 2021Theory of computation · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Network and information security
3 papers |
Hardware security and side channels · 100% | |
| Software engineering, system software, and programming languages
2 papers |
Programming languages and type systems · 38% Concurrent programming · 38% Compilers and program optimization · 25% | |
| Computer architecture, parallel and distributed computing, and storage systems
3 papers |
Performance modeling and evaluation · 34% Cloud and datacenter computing · 34% Electronic design automation · 25% | |
| Theoretical computer science
1 paper |
Automated reasoning and model checking · 100% |
Topics — the 13 heaviest of 15, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Hardware security and side channels
trusted execution environments |
1.0 | 2 | 2024 | Specification and Verification of Strong Timing Isolation of Hardware Enclaves · CCS 2024 Nimble: Rollback Protection for Confidential Cloud Services · OSDI 2023 |
Hardware security and side channels › trusted execution environments
secure enclaves |
0.8 | 1 | 2024 | Specification and Verification of Strong Timing Isolation of Hardware Enclaves · CCS 2024 |
Hardware security and side channels › hardware attacks
side-channel and fault attacks |
0.8 | 1 | 2024 | Specification and Verification of Strong Timing Isolation of Hardware Enclaves · CCS 2024 |
Hardware security and side channels › side-channel attack
timing side channel |
0.8 | 1 | 2024 | Specification and Verification of Strong Timing Isolation of Hardware Enclaves · CCS 2024 |
Cloud and datacenter computing › cloud security
confidential cloud computing |
0.7 | 1 | 2023 | Nimble: Rollback Protection for Confidential Cloud Services · OSDI 2023 |
Performance modeling and evaluation › processor performance modeling
microarchitecture modeling |
0.7 | 1 | 2023 | Pensieve: Microarchitectural Modeling for Security Evaluation · ISCA 2023 |
Electronic design automation
high-level synthesis |
0.5 | 1 | 2021 | Effective simulation and debugging for a high-level hardware language using software compilers · ASPLOS 2021 |
Concurrent programming › memory models › weak memory models
c11 memory model |
0.4 | 1 | 2019 | Cerberus-BMC: A Principled Reference Semantics and Exploration Tool for Concurrent and Sequential C · CAV (1) 2019 |
Programming languages and type systems › language semantics
c semantics |
0.4 | 1 | 2019 | Cerberus-BMC: A Principled Reference Semantics and Exploration Tool for Concurrent and Sequential C · CAV (1) 2019 |
Programming languages and type systems
language semantics |
0.4 | 1 | 2019 | Cerberus-BMC: A Principled Reference Semantics and Exploration Tool for Concurrent and Sequential C · CAV (1) 2019 |
Concurrent programming
memory models |
0.4 | 1 | 2019 | Cerberus-BMC: A Principled Reference Semantics and Exploration Tool for Concurrent and Sequential C · CAV (1) 2019 |
Automated reasoning and model checking › model checking
bounded model checking |
0.4 | 1 | 2019 | Cerberus-BMC: A Principled Reference Semantics and Exploration Tool for Concurrent and Sequential C · CAV (1) 2019 |
Hardware security and side channels › microarchitectural attacks › transient execution attack
speculative execution attack |
0.2 | 1 | 2023 | Pensieve: Microarchitectural Modeling for Security Evaluation · ISCA 2023 |
Methods — techniques the papers use, named apart from their topics
compiler technology · 1.0reference semantics · 0.8formal verification · 0.8bounded model checking · 0.8
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2024 | Specification and Verification of Strong Timing Isolation of Hardware EnclavesabstractThe process isolation enforceable by commodity hardware and operating systems is too weak to protect secrets from malicious code running on the same machine: attacks exploit timing side channels derived from contention on shared microarchitectural resources to extract secrets. With appropriate hardware support, however, we can construct isolated enclaves and safeguard independent processes from interference through timing side channels, a step towards confidentiality and integrity guarantees. Stella Lau, Thomas Bourgeat, Clément Pit-Claudel, Adam Chlipala |
CCS | 1 |
| 2023 | Pensieve: Microarchitectural Modeling for Security EvaluationabstractTraditional modeling approaches in computer architecture aim to obtain an accurate estimation of performance, area, and energy of a processor design. With the advent of speculative execution attacks and their security concerns, these traditional modeling techniques fall short when used for security evaluation of defenses against these attacks. Thomas Bourgeat, Stella Lau, Mengjia Yan 0001 |
ISCA | 3 |
| 2023 | Nimble: Rollback Protection for Confidential Cloud Services
Sebastian Angel, Aditya Basu, Weidong Cui, Trent Jaeger, Stella Lau, Srinath Setty, Sudheesh Singanamalla |
OSDI | 5 |
| 2021 | Effective simulation and debugging for a high-level hardware language using software compilersabstractRule-based hardware-design languages (RHDLs) promise to enhance developer productivity by offering convenient abstractions. Advanced compiler technology keeps the cost of these abstractions low, generating circuits with excellent area and timing properties. Clément Pit-Claudel, Thomas Bourgeat, Stella Lau, Arvind 0001, Adam Chlipala |
ASPLOS | 3 |
| 2019 | Cerberus-BMC: A Principled Reference Semantics and Exploration Tool for Concurrent and Sequential CabstractC remains central to our infrastructure, making verification of C code an essential and much-researched topic, but the semantics of C is remarkably complex, and important aspects of it are still unsettled, leaving programmers and verification tool builders on shaky ground. This paper describes a tool, Cerberus-BMC, that for the first time provides a principled reference semantics that simultaneously supports (1) a choice of concurrency memory model (including substantial fragments of the C11, RC11, and Linux kernel memory models), (2) a modern memory object model, and (3) a well-validated thread-local semantics for a large fragment of the language. The tool should be useful for C programmers, compiler writers, verification tool builders, and members of the C/C++ standards committees. Stella Lau, Victor B. F. Gomes, Kayvan Memarian, Jean Pichon-Pharabod, Peter Sewell |
CAV (1) | 1 |