Field-programmable gate array (FPGA) is a preferred solution for a CMOS image sensor (CIS) automatic test equipment (ATE) because it provides fast upgradability for the timely testing of CIS products using a new interface protocol. However, implementing a Mobile Industry Processor Interface (MIPI) C-PHY receiver to receive images from the CIS in an FPGA can be challenging due to the use of three wires, three distinct voltage levels, and the requirements of fast clock data recovery (CDR) lock time and wide CDR tracking bandwidth. To overcome these challenges, we have developed an FPGA-only MIPI C-PHY receiver that utilizes a blind oversampling CDR technique, which offers fast CDR lock time and wide CDR bandwidth. We used an Altera Stratix 10 GX FPGA as an oversampling device by operating its transceiver in a lock-to-reference-clock mode. We developed a parallel gate-based clock recovery algorithm and a fork and join-based data decision algorithm. As a result, we were able to test CIS wafers at symbol rates of up to 3.5 Giga-symbols per second, achieving performance comparable to that of sophisticated ASIC-based CIS ATEs.

For the testing of memory chips, automatic test equipment (ATE) uses pattern program to generate a bit vector for each clock. Pattern programs are not portable across different ATEs, requiring a different program for each ATE, even when they test the same memory chip. Many solutions and in-house tools have been proposed for this portability problem, but they were not completely successful. This paper proposes PaTran, a software translation platform for pattern programs. PaTran employs intermediate representation (IR) based on the pattern itself, generated by simulating the source pattern program. It synthesizes the target program by reconstructing the program statements from the IR. Since the IR size is huge for product-level programs, PaTran employs a concise form of IR, embedded with repetition information. Implementation of PaTran is based on the web and server-client model.

An Intermediate Representation (IR) used by compilers is normally generated statically , as a result of parsing or analyzing the source program. This paper proposes a completely different type of IR, generated as a result of running the source program, the output-based IR . There is a practical translation problem where such an IR is useful, in the domain of test-pattern programs . Test-pattern programs run on ATE (automatic test equipment), a special embedded system to test semiconductors such as DRAMs. They generate a pattern for each clock, a bit vector input to the pins of the chip. One issue is that different ATEs require different programming since each ATE manufacturer has its own programming language. Nonetheless, we should be able to test a memory chip on different ATEs as long as they generate the same patterns with the same speed. Therefore, a memory chipmaker wants to make a pattern program portable across ATEs, to fully utilize their ATE resources. One solution is translating between pattern programs, for which we need an IR since there are multiple source ATEs and target ATEs. Instead of a conventional, static IR, we propose using the output pattern itself as an IR. Since the pattern is independent of ATEs and easily obtainable, the output-based IR obviates designing a static IR considering all ATE programming languages and hardware differences. Moreover, we might synthesize a better target program from the IR, more optimized to the target ATE. However, the full pattern generated by a product-level pattern program is huge, so we propose using an IR of abbreviated patterns, annotated with the repetition information obtained while executing the source program. Our experimental results with product-level pattern programs show that our approach is feasible.