Thermoelectric cooling technology holds great promise as a spot-cooling solution for the VLSI circuits. Typically, it is combined with a forced convection cooler, such as a fan to achieve effective thermal management. The optimal driving current for the thermoelectric coolers and fan rotation speed play a crucial role in minimizing cooling power consumption while ensuring safe operating temperatures for the VLSI chip dies. Various software-based optimization frameworks have been proposed to calculate the near-optimal values in real time. Nonetheless, these frameworks suffer from several limitations, including slow runtime, high power consumption, costly optimization software license, and the need for a separate computer to execute the optimization software. This article presents a hardware-friendly neural network (NN)-based optimizer that can learn from the functionality of a software optimizer. In order to train the NN model, a self-supervised learning strategy is employed to generate the desired labeled data. Simulation results demonstrate that the proposed model successfully meets the thermal constraints across all the tested benchmarks, with an overall system cooling power consumption increase of only 3.6% compared to a software optimizer. Furthermore, the hardware implementation of the proposed model proves to be more than five orders of magnitude faster than the software-based optimizer, consuming a negligible amount of power while occupying a small die area.

An online interconnect BIST for detecting and avoiding interconnect faults is proposed in this paper. This BIST structure is built upon a new shielding method, the required hardware of which is reutilized in transmitting redundant test data across the interconnect for testing it. Together, BIST and the shielding parts, provide an integrated and novel interconnect testing and crosstalk fault-avoidance platform that share the same hardware. Our proposed integrated technique is modeled in SPICE to evaluate its functionality in terms of avoiding crosstalk faults, and online detection of those that cannot be avoided. We show that faults due to crosstalk are reduced by 49%, and those that still remain are 100% detected.

Crosstalk noise due to the electromagnetic coupling between wires adversely affects VLSI circuit performance. This makes interconnect testing an important issue in reliability evaluation that causes extra area and hardware overhead. In this paper, we present a novel test methodology that we refer to as Test Adapted Shielding (TAS) in order to improve testing challenges and also to optimize crosstalk noise. The test structure of TAS is designed to improve circuit performance by insertion of modified shield lines. The developed hardware for test data is smart enough to avoid aggregation over victim lines in crosstalk. Besides, the TAS test methodology is optimized in power consumption, complexity, fault occurrence, and fault detection. The proposed technique is implemented in HSPICE and MATLAB and the extracted results are used to evaluate its functionality. We show that crosstalk noise is decreased by about 49% and test coverage is 100% for negative and positive glitches.