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Pavithra Balaji

dblp:248/4668 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2019
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Software engineering, system software, and programming languages
1 paper
Concurrent programming · 77% Compilers and program optimization · 23%

Topics — the 2 heaviest of 2, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Concurrent programming
transactional memory
0.412019
Simplifying Transactional Memory Support in C++ · ACM Trans. Archit. Code Optim. 2019
Compilers and program optimization › compiler construction
compiler support for transactional memory
0.112019
Simplifying Transactional Memory Support in C++ · ACM Trans. Archit. Code Optim. 2019

Methods — techniques the papers use, named apart from their topics

hardware transactional memory · 0.4executor-based transaction execution · 0.4
YearPublicationVenuePosition
2019 Simplifying Transactional Memory Support in C++
abstract
C++ has supported a provisional version of Transactional Memory (TM) since 2015, via a technical specification. However, TM has not seen widespread adoption, and compiler vendors have been slow to implement the technical specification. We conjecture that the proposed TM support is too difficult for programmers to use, too complex for compiler designers to implement and verify, and not industry-proven enough to justify final standardization in its current form. To address these problems, we present a different design for supporting TM in C++. By forbidding explicit self-abort, and by introducing an executor-based mechanism for running transactions, our approach makes it easier for developers to get code up and running with TM. Our proposal should also be appealing to compiler developers, as it allows a spectrum of levels of support for TM, with varying performance, and varying reliance on hardware TM support in order to provide scalability. <?tight?>While our design does not enable some of the optimizations admitted by the current technical specification, we show that it enables the implementation of robust support for TM in a small, orthogonal compiler extension. Our implementation is able to handle a wide range of transactional programs, delivering low instrumentation overhead and scalability and performance on par with the current state of the art. Based on this experience, we believe our approach to be a viable means of reinvigorating the standardization of TM in C++.
Pantea Zardoshti, Tingzhe Zhou, Pavithra Balaji, Michael L. Scott, Michael F. Spear
ACM Trans. Archit. Code Optim.3