Demo Data from SIGIR 2026 / reviewers in the wild / expert
Xianhao He
dblp:248/5528
· DBLP profile ↗
3ranked-venue papers
2as first author
2since 2021 · last 2025
0000-0001-7348-1157ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 1 first-author · 2 since 2021Artificial intelligence and machine learning · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Software engineering, system software, and programming languages
2 papers |
Compilers and program optimization · 100% | |
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Processor architecture and microarchitecture · 54% Performance modeling and evaluation · 46% |
Topics — the 3 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Compilers and program optimization
code generation |
0.9 | 1 | 2025 | An Input-Aware Sparse Tensor Compiler Empowered by Vectorized Acceleration · DAC 2025 |
Compilers and program optimization › sparse computation
sparse tensor compilation |
0.9 | 1 | 2025 | An Input-Aware Sparse Tensor Compiler Empowered by Vectorized Acceleration · DAC 2025 |
Processor architecture and microarchitecture
chip multiprocessor |
0.3 | 1 | 2025 | An Input-Aware Sparse Tensor Compiler Empowered by Vectorized Acceleration · DAC 2025 |
Methods — techniques the papers use, named apart from their topics
vectorization · 1.7sparse format design · 1.7machine learning-based performance prediction · 1.5compiler instrumentation · 1.5
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | An Input-Aware Sparse Tensor Compiler Empowered by Vectorized AccelerationabstractSparsity is widely prevalent in real-world applications, yet existing compiler optimizations and code generation techniques for sparse computations remain underdeveloped. Sparse matrix-matrix multiplication (SpMM) is a representative operator in sparse computations, whose performance is often limited by the design of sparse formats and the extent of hardware architecture optimization. Most existing solutions achieve highperformance SpMM through two approaches: (1) meticulously designed kernels and specialized sparse formats, which require extensive manual effort, or (2) tensor compilers that support code generation, though these typically offer limited support for sparse patterns, making it challenging to adapt to complex sparsity patterns in practical applications. This paper presents SpMMTC, an input-aware sparse tensor compiler. Given a sparse matrix as input, SpMMTC analyzes its non-zero distribution and generates a vectorized kernel optimized for SpMM on the specific matrix. We evaluated SpMMTC on various workloads. It achieves speedups of 1.21 x to 2.97 x over state-of-the-art methods such as TACO, TVM, and ASpT on different multi-core processors. It also provides a speedup of up to $\mathbf{1. 5 2 x}$ for sparse MobileNetV1 inference on the edge device. Xianhao He, Haotian Wang 0006, Jiapeng Zhang 0001, Wangdong Yang, Anthony T. Chronopoulos, Kenli Li 0001 |
DAC | 1 |
| 2024 | COALA: A Compiler-Assisted Adaptive Library Routines Allocation Framework for Heterogeneous SystemsabstractExperienced developers often leverage well-tuned libraries and allocate their routines for computing tasks to enhance performance when building modern scientific and engineering applications. However, such well-tuned libraries are meticulously customized for specific target architectures or environments. Additionally, the performance of their routines is significantly impacted by the actual input data of computing tasks, which often remains uncertain until runtime. Accordingly, statically allocating these library routines may hinder the adaptability of applications and compromise performance, particularly in the context of heterogeneous systems. To address this issue, we propose the Compiler-Assisted Adaptive Library Routines Allocation (COALA) framework for heterogeneous systems. COALA is a fully automated mechanism that employs compiler assistance for dynamic allocation of the most suitable routine to each computing task on heterogeneous systems. It allows the deployment of varying allocation policies tailored to specific optimization targets. During the application compilation process, COALA reconstructs computing tasks and inserts a probe for each of these tasks. Probes serve the purpose of conveying vital information about the requirements of each task, including its computing objective, data size, and computing flops, to a user-level allocation component at runtime. Subsequently, the allocation component utilizes the probe information along with the allocation policy to assign the most optimal library routine for executing the computing tasks. In our prototype, we further introduce and deploy a performance-oriented allocation policy founded on a machine learning-based performance evaluation method for library routines. Experimental verification and evaluation on two heterogeneous systems reveal that COALA can significantly improve application performance, with gains of up to 4.3x for numerical simulation software and 4.2x for machine learning applications, and enhance system utilization by up to 27.8%. Qinyun Tsai, Guanghua Tan, Wangdong Yang, Xianhao He, Yuwei Yan, Keqin Li 0001, Kenli Li 0001 |
IEEE Trans. Computers | 4 |
| 2019 | Spatial Attention Network for Few-Shot Learning
Xianhao He, Peng Qiao, Yong Dou, Xin Niu 0002 |
ICANN (2) | 1 |