The wireless implantable/intracavity micromanometer (WIMM) system was designed to fulfill the unmet need for a chronic bladder pressure sensing device in urological fields such as urodynamics for diagnosis and neuromodulation for bladder control. Neuromodulation in particular would benefit from a wireless bladder pressure sensor which could provide real-time pressure feedback to an implanted stimulator, resulting in greater bladder capacity while using less power. The WIMM uses custom integrated circuitry, a MEMS transducer, and a wireless antenna to transmit pressure telemetry at a rate of 10 Hz. Aggressive power management techniques yield an average current draw of 9μA from a 3.6-Volt micro-battery, which minimizes the implant size. Automatic pressure offset cancellation circuits maximize the sensing dynamic range to account for drifting pressure offset due to environmental factors, and a custom telemetry protocol allows transmission with minimum overhead. Wireless operation of the WIMM has demonstrated that the external receiver can receive the telemetry packets, and the low power consumption allows for at least 24 hours of operation with a 4-hour wireless recharge session.

Cardiotocography is used to monitor the effect of contractions on fetal heart rate (FHR) and is used in the final trimester of pregnancy to detect fetal distress. This simple and efficient (patent-pending) architecture for Cardiotocography employs the Doppler technique to measure Fetal Heart Rate (FHR) and is scalable to any number of FHR monitors. The Doppler circuitry is designed for low cost and low power consumption to facilitate portability and compatibility with wireless data transmission. Measured results indicate performance consistent with conventional bedside systems, i.e. 8 bits of resolution with update rates ≥2 samples per second.

This paper presents the amplifier and stimulator circuits, as well as 50-Omega antenna driver, that augment a multichannel, wireless sensor interface platform IC for use in neurodynamic studies of a sea animal, Aplysia Californica. The prototype chip, including the platform and 2-channel neurodynamic interface circuits, has been fabricated in a 0.5-mum CMOS process, occupies an active area of just 0.7 mm2and consumes 3.56 mW. This would allow 120 hours of recording using 160mAh lithium ion battery. Test results of the interface circuits are presented and exhibit the desired performance

We propose a new built-in current sensor (BICS) to detect single event upsets (SEUs) in SRAM. The BICS is designed and validated for 100 nm process technology. The BICS reliability analysis is provided for process, voltage and temperature variations, and power supply noise. The BICS detects various shapes of current pulses generated due to particle strike. The BICS power consumption and area overhead are also provided. The BICS is found to be very reliable for process, voltage and temperature variations and under stringent noise conditions.

Describes the development of an autonomous hybrid micro-robot that uses legs for propulsion and support of the rear half of the body and uses a pair of wheels for support of the front half. McKibben artificial muscles actuate the legs and the compressed air that activates the actuators is generated by an on-board power plant comprising a pair of lithium batteries powering a gear motor driven air compressor. The control is also onboard in the form of a PIC that controls the actuators through four three-way valves that each consists of a pair of MEMS devices.

The monopod hopper described fits into a cube that is 5 cm on a side, is autonomous, and is designed to be statically stable and passively dynamically stable. Hopping is achieved through the excitation of a spring-mass system at its resonant frequency. Simulations were extensively used to finalize the design, before construction of the robot. The hopper, although having no active directional control, is able to climb steps up to 1 mm, travel at a rate of 1.5 body lengths per second for an average of over 225 cm before deviating significantly from its original course, and can operate up to 45 min before depleting the energy stored in the batteries.

Current state-of-the-art speech recognition systems are based on dynamic time warping (DTW) techniques in which the dominant computational task is input/reference word template matching and input/reference word non-linear time registration. A systolic array wafer scale architecture is presented which exploits the parallelism and local interconnect properties of this computation. The array executes either isolated or connected word recognition using either LPC or spectrally based templates. Restructurable VLSI (RVLSI) technology is being used to implement such an array comprised of 65 bit-serial arithmetic processing elements on a monolithic silicon 3" wafer. Speech recognition systems based on the RVLSI circuits are projected to be capable of supporting real-time vocabularies as large as 12,000 words.