The authors present a novel architecture for a high-speed pseudo vector processor based on a superscalar pipeline. Without using cache memory, the proposed architecture is able to overcome the penalty of memory access latency by introducing register windows with register preloading and pipelined memory. One outstanding feature of the proposed architecture is that it is upwardly compatible with existing scalar architectures. Performance evaluation of the proposed architecture using the Livermore Loop Kernels shows over 6 times higher performance than a usual superscalar processor and 1.2 times higher performance than a hypothetical extended model with a cache prefetching technique with a memory access latency of 20 CPU clock cycles. List vectors are also effectively handled in a similar architecture.>

The HITACHI supercomputer S-820 has been developed as Hitachi's top end supercomputer. It is also rated as one of the most powerful supercomputers in the world.

The HITACHI supercomputer S-820 system has been developed as Hitachi's top end supercomputer. It is also rated as one of the most powerful supercomputers in the world.Among the vector instructions which supercomputers support, summation type vector instructions and iteration type vector instructions are not suitable for parallel processing, since elements to be processed are not independent in these instructions. The S-820 employs high-speed processing schemes for summation type vector instructions and iteration type vector instructions; the performance of summation type instructions is enhanced by high-speed post-processing scheme and the performance of iteration type instructions is enhanced by high-speed parallelizing scheme for iteration arithmetic.Thanks to these schemes, the execution speeds for Kernel 3 and Kernel 4 of the Lawrence Livermore Laboratory's 24 Kernels become 838.7 MFLOPS and 258.5 MFLOPS respectively, and those for Kernel 5, Kernel 6 and Kernel 11 of the Lawrence Livermore Laboratory's 14 Kernels become 114.6 MFLOPS, 111.8 MFLOPS and 98.4 MFLOPS, respectively.

A new relational database system architecture based on a vector processing method is presented. The similarity between table and vector structures was studied. This similarity implies that vector processors have high potential for the improvement of Relational Data Base Management System (RDBMS) performance. In commercial RDBMSs, however, data records are internally organized in complex pointer structures, to which vector processing is not directly applicable. We propose a new vectorization method by which data in the pointer structures are dynamically rearranged into vector form, and collectively processed using a pipelined vector processor. A new pipelined vector processor called an Integrated Database Processor (IDP) which is particularly suitable for our vectorization strategy was developed. IDP is designed as an optional hardware for a general purpose computer. The vectorization method and IDP are applied to Hitachi's new, recently-announced, commercial RDBMS (called RDB1/IDP). In this paper, the vectorization method and the architecture of IDP are described. The performance improvement is also described and analyzed.