Federated learning (FL) in unmanned aerial ve-hicles (UAVs) networks demands considerable communication resources to transfer model data between the central server and UAVs (FL clients). However, different UAVs may have different communication capabilities due to the UAV's maneuverability and heterogeneity, where limited communication resource could be bottle neck for FL performance. In this paper, we first introduce a knowledge distillation based approach that places two different models with different sizes, namely the teacher model and student model, for FL client to make a trade-off between the FL performance and communication cost. Then, we propose a novel model switching method to switch between the teacher model and student model to adapt to the dynamic feature of UAV networks. Specifically, considering available communication bitrate and learning accuracy, we design a threshold-based model switching algorithm (TBMSA) and determine the threshold based on the k-means method (DTBKM) to accurately and quickly determine the switching point. In addition, for the knowledge transfer between models, we design a knowledge inheritance based on a transfer learning (KIBTL) algorithm, which transfers knowledge from one model to another. Experiments show that the proposed model switching algorithm achieves significant performance improvements as compared to existing baselines.

By enabling direct communications between nearby user equipment (UE), device‐to‐device (D2D) communication has become one of the key technologies in 5th generation (5G) mobile networks. D2D communication brings new communication opportunities for mobile devices, especially in a highly dense network. In this paper, D2D communication in the unlicensed spectrum, namely, D2D‐Unlicensed (D2D‐U), is discussed. The use of unlicensed frequency bands can ease the shortage of spectrum resources and improve network performance. However, the D2D‐U in 5G has significant effects on the network performance of existing unlicensed networks sharing the same frequency bands, such as Wi‐Fi and Bluetooth. Therefore, it is necessary to design a fair coexistence scheme for D2D‐U. To understand the coexistence problem, in this paper, we first formulate the network performance of D2D‐U and Wi‐Fi under two different coexistence schemes, namely, listen before talk (LBT) and duty cycle mechanism (DCM). Then, we use computer simulations to investigate a mode selection scheme that switches between these two schemes and point out the best possible solution for the coexistence between D2D‐U and Wi‐Fi.

Nowadays, fifth-generation (5G) technology is promoted to support massive data transmissions and low-latency communications, which enables diverse vehicular applications. There have been some studies discussing the use of vehicle clustering to save scarce spectrum resources, and prevent network congestions in hybrid cellular/IEEE 802.11p vehicular environments. However, different types of applications could have different levels of quality-of-service (QoS) requirements, and thus this issue should be considered in the clustering of vehicles. We propose a novel vehicle clustering scheme that utilizes the global view and programmable advantage of software defined networking (SDN) technology to conduct an efficient clustering in vehicular environments. The proposed scheme first classifies the existing applications to three different types, the delay-sensitive type, traffic-intensive type, and computation-intensive type, according to the QoS requirements. Then the scheme forms three different clusters based on this classification to satisfy the QoS requirement for each type. We use computer simulations to show the advantage of the proposed scheme over the conventional approach.

The Delay Tolerant Network (DTN) is a network architecture that plays an important role in intermittently connected networks. DTNs can support transmissions between clients even there are no end-to-end connections by using “store-carry-forward” mechanism, where some nodes called ferry nodes could be employed into DTN to enhance the network performance. In this paper, we use Unmanned Aerial Vehicles (UAVs) to act as ferry nodes, and a probabilistic routing protocol based on the encounter connection time between nodes is proposed. The proposed protocol not only considers the efficiency of message transmission but also the reliability between connected nodes. The proposed protocol and some existing protocols are compared and analyzed using ONE simulator. The simulation results show that the proposed protocol increases the delivery probability and reduces the average latency.

Device-to-Device (D2D) communication, which enables direct connection between the nearby user equipments (UEs), is one of the key technologies in 5G network. In this paper, D2D communication on the unlicensed spectrum, namely, D2D-U is discussed. D2D system performance can be efficiently enhanced by utilizing the unlicensed band. However, it has a huge impact on the performance of other unlicensed networks. Therefore, the fairness of the coexistence scheme is a key problem for D2D-U. To solve the coexistence problem, two access schemes called Listen Before Talk (LBT) and Duty Cycle Mechanism (DCM) have been discussed extensively. D2D users choose the transmission mode according to transmission environments. In this paper, we discuss the performance of these two modes. Furthermore, the problem of how to access the unlicensed band with combination of these two modes is also discussed.

A method for system resource management of a cloud-based disaster recovery is proposed. This method can determine whether system performance achieves the "recovery point objective" (RPO) or not. It is also necessary to resize resources for satisfying required performance at lower cost. Therefore, a formula for simulating system performance is established. The results of the simulation show it is possible to determine an appropriate system size that achieves RPO as well as minimizes amount of system resources. It is demonstrated that no error between the experimentally measured and simulated recovery points exists at peak workload. It is thus concluded that the proposed simulation is accurate enough. Also, it is estimated that 89% of system resource cost could be reduced in comparison to the case that the disaster recovery system is designed to fit a peak workload.

We propose a vehicle-to-roadside communication protocol based on a distributed clustering algorithm where a coalitional game approach is used to stimulate the vehicles to join a cluster, and a fuzzy logic algorithm is employed to generate stable clusters by taking into account multiple metrics of vehicle velocity, moving pattern, and signal qualities between vehicles. A reinforcement learning algorithm with game theory-based reward discount is employed to guide each vehicle to select the route which can maximize the whole network performance. We conduct extensive computer simulations to show the performance advantage of the protocol over other approaches.

A huge amount of data is being generated and accumulated in data centers, which leads to an important increase in the required energy consumption to analyze these data. Thus, we must consider the redesign of current computer systems architectures to be more friendly to applications based on distributed algorithms that require a high data transfer rate. Novel computer architectures that introduce dedicated accelerators to enable near-data processing have been discussed and developed for high-speed big-data analysis. In this work, we propose a computer system with an FPGA-based accelerator, namely, interconnected-FPGAs, which offers two advantages: (1) direct data transmission and (2) offloading computation into data-flow in the FPGA. In this article, we demonstrate the capability of the proposed interconnected-FPGAs system to accelerate join operations in a relational database. We developed a new parallel join algorithm, PPJoin, targeted to big-data analysis in a shared-nothing architecture. PPJoin is an extended version of the NUMA-based parallel join algorithm, created by overlapping computation by multicore processors and data communication. The data communication between computational nodes can be accelerated by direct data transmission without passing through the main memory of the hosts. To confirm the performance of the PPJoin algorithm and its acceleration process using an interconnected-FPGA platform, we evaluated a simple query for large tables. Additionally, to support availability, we also evaluated the actual benchmark query. Our evaluation results confirm that the PPJoin algorithm is faster than a software-based query engine by 1.5--5 times. Moreover, we experimentally confirmed that the direct data transmission by interconnected FPGAs reduces computational time around 20% for PPJoin.

Decentralized communication technologies (i.e., ad hoc networks) provide more opportunities for emerging wireless Internet of Things (IoT) due to the flexibility and expandability of distributed architecture. However, the performance degradation of wireless communications with the increase of the number of hops becomes the main obstacle in the development of decentralized wireless IoT systems. The main challenges come from the difficulty in designing a resource and energy efficient multihop communication protocol. Transmission control protocol (TCP), the most frequently used transport layer protocol for achieving reliable end-to-end communications, cannot achieve a satisfactory result in multihop wireless scenarios as it uses end-to-end acknowledgment which could not work well in a lossy scenario. In this paper, we propose a multihop data delivery virtualization approach which uses multiple one-hop reliable transmissions to perform multihop data transmissions. Since the proposed protocol utilizes hop-by-hop acknowledgment instead of end-to-end feedback, the congestion window size at each TCP sender node is not affected by the number of hops between the source node and the destination node. The proposed protocol can provide a significantly higher throughput and shorter transmission time as compared to the end-to-end approach. We conduct real-world experiments as well as computer simulations to show the performance gain from our proposed protocol.

Vehicular ad hoc networks (VANETs) have been attracting interest for their potential roles in intelligent transport systems (ITS). In order to enable distributed ITS, there is a need to maintain some information in the vehicular networks without the support of any infrastructure such as road side units. In this paper, we propose a protocol which can store the data in VANETs by transferring data to a new carrier (vehicle) before the current data carrier is moving out of a specified region. For the next data carrier node selection, the protocol employs fuzzy logic to evaluate instant reward by taking into account multiple metrics specifically throughput, vehicle velocity, and bandwidth efficiency. In addition, a reinforcement learning-based algorithm is used to consider the future reward of a decision. We use theoretical analysis and computer simulations to evaluate the proposed protocol.

We propose a context-aware routing protocol for vehicular ad hoc networks (VANETs). Two types of context information is considered in this paper specifically communication type (broadcast or unicast) and packet size. The proposed protocol constructs route based on virtual clustering which only exchanges beacon messages in one-hop neighborhood area. The packets are forwarded by the cluster heads, and the last 2-hop route is optimized by using a reinforcement learning algorithm which can attain good performance with low overhead. The advantage of the proposed protocol is shown by using computer simulations.

One of a critical design issues for implementing handshake-join hardware is result collection performed by a merging network. To address the issue, we introduce an adaptive merging network. Our implementation achieves over 3 million tuples per second when the selectivity is 0.1. The proposed implementation attains up to 5.2x higher throughput than original handshake-join hardware. In this demonstration, we apply the proposed technique to filter out malicious packets from packet streams. To the best of our knowledge, our system is the fastest handshake join implementation on FPGA.

This paper proposes a processor architecture for DR-SPE, a dynamic reconfigurable stream processing engine. DR-SPE is special-purpose hardware for stream data processing, which achieves high processing performance by exploiting parallelism in the target query. It also handles query registration and execution order of operations at runtime. Available operations in DR-SPE are the same as those in Streams on Wires. In this paper, DR-SPE is implemented on a FPGA XC6VLX240T-1, and its performance is evaluated. The results of the evaluation show that DR-SPE achieves register modification within 506 μsec when the configuration path is driven at 1 Mbps, which is not achieved by Streams on Wires. DR-SPE also achieves flexibility and can support complicated queries by providing 10 × 10 operation units tiled onto an FPGA. DR-SPE achieves comparable operation throughput with Streams on Wires at the expense of requiring more LUTs.

Multi and many-core applications are sensitive to interprocessor communication latencies, suggesting the need for low-latency on-chip networks. We propose a low-latency router architecture that predicts the output channel to be used by the next packet transfer and speculatively completes the switch arbitration to reduce communication latency. The packets coming into the prediction routers are transferred without waiting for the routing computation and switch arbitration if the prediction hits. Thus, the primary concern for reducing communication latency is the hit rates of the prediction algorithms, which vary based on network environments, such as the network topology, routing algorithm, and traffic pattern. Although typical low-latency routers that skip one or more pipeline stages use a bypass data path that is based on a static or single bypassing policy (e.g., accelerating the packets moving in the same dimension), our prediction router architecture predictively forwards packets based on the prediction algorithm selected from among several candidates in response to the network environment. We analyze the prediction hit rates of five prediction algorithms on meshes, tori, fat trees, and Spidergons. Then, we present four case studies, each of which assumes different many-core architectures. We implemented the prediction routers for each case study by using a 45 nm CMOS process, and evaluated them in terms of the prediction hit rate, zero-load latency, hardware amount, and energy consumption. A typical prediction router with two or three predictors shows that although the area and energy are increased by 4.8-12.0 percent and 5.3 percent, respectively, up to 89.8 percent of the prediction hit rate is achieved in real applications, which provides favorable trade-offs between modest hardware/energy overheads and significant latency saving.

Network-on-Chips (NoCs) are quite latency sensitive, since their communication latency strongly affects the application performance on recent many-core architectures. To reduce the communication latency, we propose a low-latency router architecture that predicts an output channel being used by the next packet transfer and speculatively completes the switch arbitration. In the prediction routers, incoming packets are transferred without waiting the routing computation and switch arbitration if the prediction hits. Thus, the primary concern for reducing the communication latency is the hit rates of prediction algorithms, which vary from the network environments, such as the network topology, routing algorithm, and traffic pattern. Although typical low-latency routers that speculatively skip one or more pipeline stages use a bypass datapath for specific packet transfers (e.g., packets moving on the same dimension), our prediction router predictively forwards packets based on a prediction algorithm selected from several candidates in response to the network environments. In this paper, we analyze the prediction hit rates of six prediction algorithms on meshes, tori, and fat trees. Then we provide three case studies, each of which assumes different many-core architecture. We have implemented a prediction router for each case study by using a 65 nm CMOS process, and evaluated them in terms of the prediction hit rate, zero load latency, hardware amount, and energy consumption. The results show that although the area and energy are increased by 6.4-15.9% and 8.0-9.5% respectively, up to 89.8% of the prediction hit rate is achieved in real applications, which provide favorable trade-offs between the modest hardware/energy overheads and the latency saving.

Concentration index filter is a kind of spatial filters of images, and its typical application is diagnosis from medical images. This paper presents a dedicated computing engine for concentration index filtering. Original algorithm is modified to extract full parallelism and data width is optimized for maximizing clock speed and minimizing hardware scale. Evaluation results reveal that the system runs 100 times faster than current workstation and enables real-time diagnosis.

Thread Level Parallelism (TLP) is the most promising way to the futur e high-p erformance microprocessors. When a sequential program code is speculatively execute din a multithreaded manner, it is natural that each speculative thread follows the control ow of the program. Based on this backgr ound, various studies have b en performed on speculative multithreading, following control ow graph. This pap erprop osesa new execution model that aims at the speedup of the execution of usual sequential program codes by sp eculatively executing the multiple contr ol ows in parallel. Further, this paper shows the thread contr olmechanism and the inter-thread communication facility requir ed for the realization of the model. F or the evaluation of our model, the cycle-b asedinstruction-level simulator has been developed. We evaluate our model with simple benchmark programs and show the e ectiveness of our model especially, for the case where the speculation by single c ontr ol ow is di cult to sp eedup the programs.

In order to improve network performance, a variety of adaptive routing algorithms have been proposed. Recent research focuses on their implementation costs, as well as the performance to enhance their practical applications. The paper proposes the Recover-x adaptive router, which limits escape message candidate in a blocked or deadlocked configuration. This limitation simplifies the routing logic and offers a chance to balance the usage between adaptive and non-adaptive channels. The cost and performance of four wormhole routers based on Verilog-HDL designs were compared. Synthesis results for the chosen gate array technology show that the Recover-x router attains a fast operating speed and low-latency, with high-bandwidth communication performance.

Our research investigates cost and performance characteristics for wormhole routers based on HDL designs. Comparison for dimension order routers and turn model based adaptive routers leads to the following conclusions: (1) static and additional routing information which we propose, such as prior dimension specification and in-order delivery, improves the communication performance; (2) an adaptive routing algorithm must be implemented to satisfy the objective speed of the design (the operation speed of the routers significantly affects the network performance); (3) the virtual channels cancel the improvement not only for the dimension order router but also for the naive implementation of the adaptive routers when they degrade the operation speed.

A description is presented of the design principles and features of the A-NETL, a language for describing highly parallel programs. The authors explain the features by using an example program. They also refer to its programming environment, which includes a multiwindow-based programming support system, language processors, and a debugger.>

For mapping a task graph to a processor graph, this strategy evaluates several functions that represent some intuitively feasible properties of the graphs. Several strategies are defined to guide the mapping process, utilizing the indicated values. An allocation system has been designed and implemented based on this strategy. The experimental results indicate the following: the system can yield 2.14 times better allocation than an arbitrary allocation; it is difficult to select a single strategy capable of providing the best solutions for a wide range of task-processor combinations; and the computation time of the allocator is reasonable. The effect of task and processor topology combinations on the allocation results is also discussed.>

A-NET is a parallel object-oriented total architecture for highly parallel computation. Starting with a computation model, the authors describe parallel constructs of the designed language, called A-NETL; the A-NETL-oriented machine instruction set architecture; the hardware organization of a node processor, which consists of a 40-bit processing element and a router; and a local operating system on each of the node processors. Statistics for the designed language and the machine are derived from experimental results.>