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Daniel Townley

dblp:250/5797 · DBLP profile ↗
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4ranked-venue papers
4as first author
2since 2021 · last 2023
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 first-authorComputer networks · 1 · 1 first-author · 1 since 2021Security and privacy · 1 · 1 first-author · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Memory systems · 78% Processor architecture and microarchitecture · 22%
Network and information security
2 papers
Systems and software security · 57% Hardware security and side channels · 43%

Topics — the 7 heaviest of 7, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems
cache
0.722022
Composable Cachelets: Protecting Enclaves from Cache Side-Channel Attacks · USENIX Security Symposium 2022
LATCH: A Locality-Aware Taint CHecker · MICRO 2019
Hardware security and side channels › side-channel attack
cache side-channel attacks
0.612022
Composable Cachelets: Protecting Enclaves from Cache Side-Channel Attacks · USENIX Security Symposium 2022
Memory systems › cache management
cache partitioning
0.612022
Composable Cachelets: Protecting Enclaves from Cache Side-Channel Attacks · USENIX Security Symposium 2022
Systems and software security › information flow tracking
dynamic information flow tracking
0.412019
LATCH: A Locality-Aware Taint CHecker · MICRO 2019
Systems and software security › information flow tracking
taint analysis
0.412019
LATCH: A Locality-Aware Taint CHecker · MICRO 2019
Processor architecture and microarchitecture
hardware-assisted security
0.412019
LATCH: A Locality-Aware Taint CHecker · MICRO 2019
Memory systems › cache
temporal locality
0.112019
LATCH: A Locality-Aware Taint CHecker · MICRO 2019

Methods — techniques the papers use, named apart from their topics

cache partitioning · 1.1fine-grained tracking · 0.8coarse-grained checking · 0.8
YearPublicationVenuePosition
2023 Secure NDN Packet Encapsulation
abstract
Packet encapsulation is a general network technique that provides an essential building block for constructing secure networks. While extensively used in IP networks over the last few decades, secure packet encapsulation remains largely unexplored in the context of Named Data Networking (NDN) networks. NDN represents a radical departure from traditional endpoint-oriented networking by making secured data the centerpiece of communication. This new data-centric design brings both advantages and new challenges for the development of secure packet encapsulation that can preserve essential properties of an NDN network, including in-network data caching and builtin multicast data delivery. In this paper, we first identify the major differences between encapsulation solution designs in IP and NDN, highlighting the ensuing challenges, both inherent and practical. We then present a novel design to achieve secure NDN data packet encapsulation, and showcase an implementation suite that enables efficient fetching of securely encapsulated data.11The views, opinions and/or findings expressed are those of the authors and should not be interpreted as representing the official views or policies of the Department of Defense or the U.S. Government. Distribution Statement “A” (Approved for Public Release, Distribution Unlimited)
Daniel Townley, Fred Douglis, Jesse Elwell, Constantin Serban, Alexander Afanasyev, Lixia Zhang 0001
ICC1
2022 Composable Cachelets: Protecting Enclaves from Cache Side-Channel Attacks
Daniel Townley, Kerem Arikan, Yu David Liu, Dmitry V. Ponomarev, Oguz Ergin
USENIX Security Symposium1
2019 SMT-COP: Defeating Side-Channel Attacks on Execution Units in SMT Processors
abstract
Recent advances in side-channel attacks put intoquestion the viability of Simultaneous Multithreading (SMT) architectures from the security standpoint. To address this problem, we propose SMT-COP-a system that eliminates all known side-channels through shared execution logic, including ports and functional units, on SMT processors. At the core of SMT-COP is a small modification to the instruction scheduling logic that allows support for both spatial and temporal partitioning of the execution units to prevent controllable contention for these resources that causes side-channel attacks. We demonstrate thatthe security benefits of SMT-COP are achieved with modest performance overhead and hardware complexity, and without relying on software support. Further performance improvements can be achieved when SMT-COP is applied selectively, and we consider three forms of such selective application: a) in response to detecting resource contention; b) in response to detecting manipulations with time measurement infrastructure; and c) in response to explicit requests by applications. This study represents a step towards making SMT processors more secure.
Daniel Townley, Dmitry V. Ponomarev
PACT1
2019 LATCH: A Locality-Aware Taint CHecker
abstract
We present LATCH (short for Locality-Aware Taint CHecker), a generalizable architecture for optimizing dynamic information flow tracking (DIFT). LATCH exploits the observation that information flows under DIFT exhibit strong temporal locality, with typical applications manipulating sensitive data during limited phases of computation. This property allows LATCH to monitor significant spans of execution using lightweight, coarse-grained checks, invoking precise, computationally intensive tracking logic only during periods of execution that involve sensitive data. LATCH implements this policy without sacrificing the accuracy of DIFT.
Daniel Townley, Khaled N. Khasawneh, Dmitry V. Ponomarev, Nael B. Abu-Ghazaleh, Lei Yu 0001
MICRO1