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Fares Elsabbagh

dblp:259/2349 · DBLP profile ↗
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4ranked-venue papers
2as first author
3since 2021 · last 2026
0009-0001-7100-0353ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4 · 2 first-author · 3 since 2021Software engineering, systems software and programming languages · 1 · 1 first-author · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
3 papers
Electronic design automation · 44% GPUs and heterogeneous computing · 20% Reconfigurable computing and FPGAs · 13%

Topics — the 9 heaviest of 11, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware verification and test
hardware verification
0.712023
Accelerating RTL Simulation with Hardware-Software Co-Design · MICRO 2023
Electronic design automation › hardware verification and test › hardware verification
RTL simulation
0.712023
Accelerating RTL Simulation with Hardware-Software Co-Design · MICRO 2023
GPUs and heterogeneous computing
GPU architecture
0.512021
Vortex: Extending the RISC-V ISA for GPGPU and 3D-Graphics · MICRO 2021
GPUs and heterogeneous computing
GPU computing
0.512021
Vortex: Extending the RISC-V ISA for GPGPU and 3D-Graphics · MICRO 2021
Processor architecture and microarchitecture › instruction set architecture › ISA extension
RISC-V ISA extension
0.512021
Vortex: Extending the RISC-V ISA for GPGPU and 3D-Graphics · MICRO 2021
Electronic design automation
hardware/software co-design
0.412020
Cash: A Single-Source Hardware-Software Codesign Framework for Rapid Prototyping · FPGA 2020
Electronic design automation
high-level synthesis
0.412020
Cash: A Single-Source Hardware-Software Codesign Framework for Rapid Prototyping · FPGA 2020
Performance modeling and evaluation › simulation › architectural simulation
simulation acceleration
0.212023
Accelerating RTL Simulation with Hardware-Software Co-Design · MICRO 2023
Reconfigurable computing and FPGAs
FPGA accelerator
0.112020
Cash: A Single-Source Hardware-Software Codesign Framework for Rapid Prototyping · FPGA 2020

Methods — techniques the papers use, named apart from their topics

hardware-software co-design · 0.7ISA extension · 0.5FPGA implementation · 0.5single-source programming · 0.4high-level synthesis · 0.4
YearPublicationVenuePosition
2026 Lotus: A Multi-FPGA Task Dataflow Architecture to Accelerate Cycle-Level Simulation
Fares Elsabbagh, Joel S. Emer, Daniel Sánchez 0003
ISCA1
2023 Accelerating RTL Simulation with Hardware-Software Co-Design
abstract
Fast simulation of digital circuits is crucial to build modern chips. But RTL (Register-Transfer-Level) simulators are slow, as they cannot exploit multicores well. Slow simulation lengthens chip design time and makes bugs more frequent.
Fares Elsabbagh, Shabnam Sheikhha, Victor A. Ying, Quan M. Nguyen, Joel S. Emer, Daniel Sánchez 0003
MICRO1
2021 Vortex: Extending the RISC-V ISA for GPGPU and 3D-Graphics
abstract
The importance of open-source hardware and software has been increasing. However, despite GPUs being one of the more popular accelerators across various applications, there is very little open-source GPU infrastructure in the public domain. We argue that one of the reasons for the lack of open-source infrastructure for GPUs is rooted in the complexity of their ISA and software stacks. In this work, we first propose an ISA extension to RISC-V that supports GPGPUs and graphics. The main goal of the ISA extension proposal is to minimize the ISA changes so that the corresponding changes to the open-source ecosystem are also minimal, which makes for a sustainable development ecosystem. To demonstrate the feasibility of the minimally extended RISC-V ISA, we implemented the complete software and hardware stacks of Vortex on FPGA. Vortex is a PCIe-based soft GPU that supports OpenCL and OpenGL. Vortex can be used in a variety of applications, including machine learning, graph analytics, and graphics rendering. Vortex can scale up to 32 cores on an Altera Stratix 10 FPGA, delivering a peak performance of 25.6 GFlops at 200 Mhz.
Blaise-Pascal Tine, Krishna Praveen Yalamarthy, Fares Elsabbagh, Hyesoon Kim
MICRO3
2020 Cash: A Single-Source Hardware-Software Codesign Framework for Rapid Prototyping
abstract
With Moore's Law coming to an end, hardware specialization and systems on chips are providing new opportunities for continuing performance scaling while reducing the energy cost of computation. However, the current hardware design methodologies require significant engineering efforts and domain expertise, making the design process unscalable. More importantly, hardware specialization presents a unique challenge for a much tighter software and hardware co-design environment to exploit domain-specific optimizations and design efficiency. In this work, we introduce Cash, a single-source hardware-software co-design framework for rapid SoC prototyping and accelerators research. Cash leverages the unique efficiency and generative attributes of Modern C++ to provide a unified development environment, aiming at closing the architecture research methodology gap. The Cash framework introduces new co-design programming abstractions that enable seamless integration with existing software from architecture research simulators to high-level synthesis.
Blaise-Pascal Tine, Fares Elsabbagh, Seyong Lee, Jeffrey S. Vetter, Hyesoon Kim
FPGA2