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Maziar Amiraskari

dblp:259/3892 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2020
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware accelerators and domain-specific architectures · 62% Electronic design automation · 38%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware accelerators and domain-specific architectures › accelerator orchestration
accelerator sharing
0.412020
Early-stage Automated Identification of Similar Hardware Implementations with Abstract-Syntax-Tree · FPGA 2020
Electronic design automation
high-level synthesis
0.112020
Early-stage Automated Identification of Similar Hardware Implementations with Abstract-Syntax-Tree · FPGA 2020
Electronic design automation › design representation
register transfer level analysis
0.112020
Early-stage Automated Identification of Similar Hardware Implementations with Abstract-Syntax-Tree · FPGA 2020

Methods — techniques the papers use, named apart from their topics

abstract syntax tree analysis · 0.4
YearPublicationVenuePosition
2020 Early-stage Automated Identification of Similar Hardware Implementations with Abstract-Syntax-Tree
abstract
The resource requirements of application-specific accelerators challenge embedded system designers who have a tight area budget but must cover a range of possible software kernels. We propose an early detection methodology (ReconfAST) to identify computationally similar synthesizable kernels to build Shared Accelerators (SAs). SAs are specialized hardware accelerators that execute very different software kernels but share the common hardware functions between them. SAs increase the fraction of workloads covered by specialized hardware by detecting similarities in dataflow and control flow between seemingly very different workloads. Existing methods use either dynamic traces or analyze register transfer level (RTL) implementations to find these similarities which require deep knowledge of RTL and time-consuming design process.
Parnian Mokri, Maziar Amiraskari, Yuelin Liu, Mark Hempstead
FPGA2