For sub-100nm processes, predictions are putting initial process yields in the single digits. At the same time, at 130nm, we saw that two chips designed with the same methodology and same design rules could deliver completely different manufacturing yields.This panel will discuss the reasons for these phenomena and talk about future trends in DFM that will need to be addressed for success below 100nm.

The inaccuracy of Elmore delay #3# for interconnect delay estimation is well-documented. However it remains a popular delay measure to drive performance optimization procedures such as wire-sizing and topology construction. This paper studies the merits of incorporating #better-than-Elmore" delay measures into the optimization process. The proposed delay metrics use a table-lookup methodtoincorporate better load modeling and approximate the e#ect of signal slew. We demonstrate that the proposed metrics exhibit a much narrower error distribution than Elmore delay, eliminating Elmore's frequent gross delay over-estimation. Finally we show the improvement in solution quality which can be had by incorporating the new metrics into a timing driven topology construction algorithm. 1 Introduction The advent of deep submicron #DSM# technology has produced a great deal of interest in CAD algorithms for interconnect delay optimization. Past work includes algorithms for bu#er ins...

Pass transistor logic (PTL) can be a promising alternative to static CMOS for deep sub-micron design. The authors motivate the need for CAD algorithms for PTL circuit design and propose decomposed BDDs as a suitable logic level representation for synthesis of PTL networks. Decomposed BDDs can represent large, arbitrary functions as a multistage circuit and can exploit the natural, efficient mapping of a BDD to PTL. A comprehensive synthesis flow based on decomposed BDDs is outlined for PTL design. They show that the proposed approach allows one to make logic-level optimizations similar to the traditional multi-level network based synthesis flow for static CMOS, and also makes possible optimizations with a direct impact on area, delay and power of the final circuit implementation which do nor have any equivalent in the traditional approach. They also present a set of heuristical algorithms to synthesize PTL circuits optimized for area, delay and power which are key to the proposed synthesis flow. Experimental results on ISCAS benchmark circuits show that the technique yields PTL circuits with substantial improvements over static CMOS designs. In addition, to the best of their knowledge this is the first time PTL circuits have been synthesized for the entire ISCAS benchmark set.

A technology dependent power optimization technique is proposed which formuhres the problem of hot spot reoktion as a variant of the engineering change (EC) problem A technique is presentedfor determining the sensitivity of circuit power dissipation tofunctional changer considering both local and global effects.This sensitivity is combined with a measure of synthesis jZexibility to identify hot regions in the circuit which have a lot offi'exibility in making functional changes andfor whom a small functional change can greatly @ect the overall power dissipation.An incompletely specified target function is constructed for the hot region such thnt any implementation sati.@ng it is expected to reduce power.A rewiring algorithm is used to solve the resulting EC problem without o#ecting circuit area, gate capacitance or delay under the unit delay mode.? Experimental results on a set of MCNC benchmark circuits show that the proposed approach con give up fo 13% reo'uction in power dissipotion with an average reaktion of 4%.

The Boolean space spanned by the primary input vectors of a combinational function may contain a large variance in minterm probabilities. By partitioning the Don't Care set into regions strongly and weakly influential upon switching activity we exploit this variance to bias area-optimization rewards reduced power dissipation. Experimental results indicate that our method can reduce power dissipation of a combinational CMOS circuit with no penalty in area.