In a traditional 2-D field-programmable gate array (FPGA), the number of routing switches increases as the number of logic gates increases, and thereby causes a decrease in the logic density. DeHon et al. demonstrated that a tree-based FPGA they proposed resolves this problem and requires only a constant number ofswitches per gate without any relation to the total number of gates. This paper presents that a multidimensional FPGA that exploits the multidimensional mesh topology also achieves asymptotically identical area efficiency to that of a tree-based FPGA. We model a multidimensional FPGA as a simple extension of the traditional 2-D and 3-D FPGAs, and realize it by embedding it onto a 2-D chip. We show a multidimensional FPGA can be embedded onto a 2-D chip with no critical increase in the amount of metal wiring. Although our embedding method causes a gap between the lengths of wire segments in different axial directions, a multidimensional FPGA indicates lower interconnection delay than a 2-D FPGA. We show that the speed advantage of a 4-D FPGA compared with a 2-D FPGA extends along with further integration and scaling of semiconductor devices by predicting maximum and average net delays.

It is shown that room-temperature CMOS, which has rarely been considered suitable for very-high-speed computer logic, can have sufficient performance to be the post-ECL (emitter-coupled logic) high-speed device when deep-submicrometer technology is available. The possibilities of CMOS are evaluated in the context of the very many factors related to computer logic. In a case study, it is shown that system performance comparable to that of the most modern large-scale computers is obtainable with room-temperature operation, assuming CMOS devices with gate length of 0.2-0.25 mu m. Further possibilities for performance improvement and the advantage of CMOS compared with other technologies are discussed.>

A wafer-scale-integration (WSI) neural network has been fabricated and evaluated. 576 digital neurons are integrated and interconnected with each other on a 5-in silicon wafer by using 0.8-μm CMOS. Neural functions are faithfully mapped to binary digital circuits. The 9-bit output and the 8-bit synapse weight of each neuron are variable. A time-sharing digital bus architecture overcomes the disadvantage of digital neuron circuits. This WSI neural network can be connected with a host computer and used for a wide range of artificial neural networks. The 16-city traveling salesman problem could be solved in less than 0.1 s by using this network. This speed was 10 times faster than a Hitachi supercomputer. Larger artificial neural networks can be realized by simply connecting WSIs