The on-line monitoring and detection of defects in laser welding is a basic manifacturing requirement in several applicative contexts, including vehicle assembly in automotive production. The speed of assembly in modern industry and the large amount of data to be acquired and elaborated pose severe real-time constraints and lead to the need of extremely short processing latencies. In this work, the implementation of time-frequency analysis algorithms on an FPGA device is shown and compared to pure software developments on different processors.

This paper describes a CORDIC-based architecture to efficiently compute the phase difference between two complex numbers. The problem of fast phase difference computation is central in many signal processing algorithms. Our main focus has been posed on the phase correlation technique applied to motion estimation. A reduced complexity solution is proposed and specifically tailored to suit the application needs. The presented algorithm has been completely implemented in 0.25 /spl mu/m standard-cell CMOS technology. As far as the performance are concerned the designed core outperforms a recently designed solution by more than 50% under area and energy standpoints.

During the last years wireless market has experienced an exponential growth. 2G systems are essentially voice-oriented: the main innovation expected from 3G ones is the ubiquitous Internet and multimedia fruition. The transition from 2G to 3G provides both opportunities and challenges: one way to make this migration as smoother as possible relies on the employment of reconfigurable architectures. In this paper a reconfigurable Rake Receiver for W-CDMA is proposed. Very promising results from the physical implementation on a XCV300E have been obtained.

Wireless Sensor Networks are an emerging phenomenon in the research community. The design and development of network architectures and nodes implementation are fostering many research activities. Due to their wide application fields and pervasive employment possibilities, the investigation of novel classes of wireless sensor nodes is of great concern. In this paper we presented a novel Power-Scalable Motion Estimation IP suitable for video-surveillance over Wireless Sensor Networks. The proposed architecture can achieve low dynamic power, good video quality and reasonable frame-rates. Moreover, it can operate on different video format and can be reconfigured both off-line and on-line. Further researches have to be accomplished in order to reduce the internal critical path, achieving better maximum frequencies performances. Moreover, new FPGA architectures must be exploited searching low-static-power devices suitable for an actual implementation of our IP on a WSN.

In the last years mobile terminals diffusion has fostered the development of new audio-visual services. Thus the possibility to employ wireless devices to exchange multimedia informations is becoming real. Beyond these attractive motivations, some critical factors are hidden: the design of wireless terminals, in fact, has to deal with limited power budgets and reduced resources availability. This paper proposes a hardware implementation of a SPIHT coprocessor, designed for mobile environments. Particular emphasis will be posed on memory requirements and their hardware implications.

An energy efficient architecture for the discrete cosine transform is presented. The proposed IP is intended to be used as the transform stage in a mobile H.263 codec. In particular, it seems well suited for an FPGA implementation since, after a complete place and route process, it is able to sustain a full-motion PAL video streaming operating at a frequency of 74 MHz with a dynamic power dissipation of just 39 mW.