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Ranggi Hwang

dblp:264/9899 · DBLP profile ↗
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7ranked-venue papers
3as first author
6since 2021 · last 2026
0000-0003-2343-586XORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 7 · 3 first-author · 6 since 2021Software engineering, systems software and programming languages · 4 · 2 first-author · 3 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
7 papers
Hardware accelerators and domain-specific architectures · 50% Cloud and datacenter computing · 28% GPUs and heterogeneous computing · 10%
Artificial intelligence
3 papers
Efficient and distributed learning · 61% Trustworthy machine learning · 31% Graph learning · 8%
Databases, data mining, and information retrieval
1 paper
Recommender systems · 100%

Topics — the 20 heaviest of 21, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware accelerators and domain-specific architectures
machine learning accelerator
2.962025
Pre-gated MoE: An Algorithm-System Co-Design for Fast and Scalable Mixture-of-Expert Inference · ISCA 2024
GROW: A Row-Stationary Sparse-Dense GEMM Accelerator for Memory-Efficient Graph Convolutional Neural Networks · HPCA 2023
DiVa: An Accelerator for Differentially Private Machine Learning · MICRO 2022
Cloud and datacenter computing
inference serving
1.322026
PASCAL: A Phase-Aware Scheduling Algorithm for Serving Reasoning-based Large Language Models · HPCA 2026
Debunking the CUDA Myth Towards GPU-based AI Systems: Evaluation of the Performance and Programmability of Intel's Gaudi NPU for AI Model Serving · ISCA 2025
Cloud and datacenter computing › inference serving
LLM serving
1.012026
PASCAL: A Phase-Aware Scheduling Algorithm for Serving Reasoning-based Large Language Models · HPCA 2026
GPUs and heterogeneous computing
preemption
1.012026
PASCAL: A Phase-Aware Scheduling Algorithm for Serving Reasoning-based Large Language Models · HPCA 2026
Cloud and datacenter computing
request scheduling
1.012026
PASCAL: A Phase-Aware Scheduling Algorithm for Serving Reasoning-based Large Language Models · HPCA 2026
Performance modeling and evaluation
benchmarking
0.912025
Debunking the CUDA Myth Towards GPU-based AI Systems: Evaluation of the Performance and Programmability of Intel's Gaudi NPU for AI Model Serving · ISCA 2025
Machine learning › Trustworthy machine learning › privacy
differentially private training
0.812024
LazyDP: Co-Designing Algorithm-Software for Scalable Training of Differentially Private Recommendation Models · ASPLOS (2) 2024
Machine learning › Efficient and distributed learning › model compression
expert offloading
0.812024
Pre-gated MoE: An Algorithm-System Co-Design for Fast and Scalable Mixture-of-Expert Inference · ISCA 2024
Machine learning › Efficient and distributed learning
model compression
0.812024
Pre-gated MoE: An Algorithm-System Co-Design for Fast and Scalable Mixture-of-Expert Inference · ISCA 2024
Recommender systems
neural recommendation
0.812024
LazyDP: Co-Designing Algorithm-Software for Scalable Training of Differentially Private Recommendation Models · ASPLOS (2) 2024
Hardware accelerators and domain-specific architectures › machine learning accelerator › DNN inference
mixture-of-experts inference
0.812024
Pre-gated MoE: An Algorithm-System Co-Design for Fast and Scalable Mixture-of-Expert Inference · ISCA 2024
Hardware accelerators and domain-specific architectures › machine learning accelerator › graph neural network accelerator
graph convolutional network accelerator
0.712023
GROW: A Row-Stationary Sparse-Dense GEMM Accelerator for Memory-Efficient Graph Convolutional Neural Networks · HPCA 2023
Hardware accelerators and domain-specific architectures › machine learning accelerator
embedding layer acceleration
0.412020
Centaur: A Chiplet-based, Hybrid Sparse-Dense Accelerator for Personalized Recommendations · ISCA 2020
Memory systems
processing-in-memory
0.412020
Centaur: A Chiplet-based, Hybrid Sparse-Dense Accelerator for Personalized Recommendations · ISCA 2020
Hardware accelerators and domain-specific architectures › machine learning accelerator
recommendation system accelerator
0.412020
Centaur: A Chiplet-based, Hybrid Sparse-Dense Accelerator for Personalized Recommendations · ISCA 2020
GPUs and heterogeneous computing
GPU memory management
0.212024
Pre-gated MoE: An Algorithm-System Co-Design for Fast and Scalable Mixture-of-Expert Inference · ISCA 2024
Machine learning › Graph learning › graph neural network
graph convolutional network
0.212023
GROW: A Row-Stationary Sparse-Dense GEMM Accelerator for Memory-Efficient Graph Convolutional Neural Networks · HPCA 2023
Privacy and data protection
differential privacy
0.212022
DiVa: An Accelerator for Differentially Private Machine Learning · MICRO 2022
Privacy and data protection › differential privacy › differentially private deep learning
DP-SGD
0.212022
DiVa: An Accelerator for Differentially Private Machine Learning · MICRO 2022
Reconfigurable computing and FPGAs › FPGA SoC
CPU-FPGA integration
0.112020
Centaur: A Chiplet-based, Hybrid Sparse-Dense Accelerator for Personalized Recommendations · ISCA 2020

Methods — techniques the papers use, named apart from their topics

noise sampling · 2.3gradient compression · 2.3differential privacy · 2.3DP-SGD · 2.3pre-gating · 1.5algorithm-system co-design · 1.5gustavson's algorithm · 1.3chain-of-thought inference · 1.0programmability assessment · 0.9microbenchmarking · 0.9software-hardware co-design · 0.7workload characterization · 0.6systolic array · 0.6
YearPublicationVenuePosition
2026 PASCAL: A Phase-Aware Scheduling Algorithm for Serving Reasoning-based Large Language Models
abstract
The emergence of reasoning-based LLMs leveraging Chain-of-Thought (CoT) inference introduces new serving challenges, as their extended reasoning phases delay user-visible output and inflate Time-To-First-Token (TTFT). Existing LLM serving frameworks fail to distinguish between reasoning and answering phases, leading to performance degradation under GPU memory constraints. We present PASCAL, a phase-aware scheduling algorithm that prioritizes reasoning to reduce TTFT while using controlled preemption and token pacing during answering to preserve Quality-of-Experience (QoE). Our hierarchical scheduler combines instance-level placement with intrainstance execution and enables dynamic migration at phase boundaries to balance load and reduce interference. Across benchmarks using DeepSeek-R1-Distill-Qwen-32B, Pascal reduces tail TTFT by up to 72 % while maintaining answering phase SLO attainment, demonstrating the importance of phaseaware scheduling for reasoning-based LLM deployment.
Eunyeong Cho, Jehyeon Bang, Ranggi Hwang, Minsoo Rhu
HPCA3
2025 Debunking the CUDA Myth Towards GPU-based AI Systems: Evaluation of the Performance and Programmability of Intel's Gaudi NPU for AI Model Serving
abstract
This paper presents a comprehensive evaluation of Intel Gaudi NPUs as an alternative to NVIDIA GPUs, which is currently the de facto standard in AI system design.First, we create microbenchmarks to compare Intel Gaudi-2 with NVIDIA A100, showing that Gaudi-2 achieves competitive performance not only in primitive AI compute, memory, and communication operations but also in executing several important AI workloads end-to-end.We then assess Gaudi NPU's programmability by discussing several softwarelevel optimization strategies to employ for implementing critical FBGEMM operators and vLLM, evaluating their efficiency against GPU-optimized counterparts.Results indicate that Gaudi-2 achieves energy efficiency comparable to A100, though there are notable areas for improvement in terms of software maturity.Overall, we conclude that, with effective integration into high-level AI frameworks, Gaudi NPUs could challenge NVIDIA GPU's dominance in * Both authors contributed equally to this research.
Yunjae Lee, Juntaek Lim, Jehyeon Bang, Eunyeong Cho, Huijong Jeong, Taesu Kim, Joonhyung Lee, Jinseop Im, Ranggi Hwang, Se Jung Kwon, Dongsoo Lee, Minsoo Rhu
ISCA10
2024 LazyDP: Co-Designing Algorithm-Software for Scalable Training of Differentially Private Recommendation Models
abstract
Differential privacy (DP) is widely being employed in the industry as a practical standard for privacy protection. While private training of computer vision or natural language processing applications has been studied extensively, the computational challenges of training of recommender systems (RecSys) with DP have not been explored. In this work, we first present our detailed characterization of private RecSys training using DP-SGD, root-causing its several performance bottlenecks. Specifically, we identify DP-SGD's noise sampling and noisy gradient update stage to suffer from a severe compute and memory bandwidth limitation, respectively, causing significant performance overhead in training private RecSys. Based on these findings, we propose LazyDP, an algorithm-software co-design that addresses the compute and memory challenges of training RecSys with DP-SGD. Compared to a state-of-the-art DP-SGD training system, we demonstrate that LazyDP provides an average 119× training throughput improvement while also ensuring mathematically equivalent, differentially private RecSys models to be trained.
Juntaek Lim, Youngeun Kwon, Ranggi Hwang, Kiwan Maeng, G. Edward Suh, Minsoo Rhu
ASPLOS (2)3
2024 Pre-gated MoE: An Algorithm-System Co-Design for Fast and Scalable Mixture-of-Expert Inference
abstract
Large language models (LLMs) based on transformers have made significant strides in recent years, the success of which is driven by scaling up their model size. Despite their high algorithmic performance, the computational and memory requirements of LLMs present unprecedented challenges. To tackle the high compute requirements of LLMs, the Mixture-ofExperts (MoE) architecture was introduced which is able to scale its model size without proportionally scaling up its computational requirements. Unfortunately, MoE’s high memory demands and dynamic activation of sparse experts restrict its applicability to real-world problems. Previous solutions that offload MoE’s memory-hungry expert parameters to CPU memory fall short because the latency to migrate activated experts from CPU to GPU incurs high performance overhead. Our proposed Pre-gated MoE system effectively tackles the compute and memory challenges of conventional MoE architectures using our algorithm-system codesign. Pre-gated MoE employs our novel pre-gating function which alleviates the dynamic nature of sparse expert activation, allowing our proposed system to address the large memory footprint of MoEs while also achieving high performance. We demonstrate that Pre-gated MoE is able to improve performance, reduce GPU memory consumption, while also maintaining the same level of model quality. These features allow our Pre-gated MoE system to cost-effectively deploy large-scale LLMs using just a single GPU with high performance.
Ranggi Hwang, Jianyu Wei, Shijie Cao, Changho Hwang, Xiaohu Tang 0003, Ting Cao 0003, Mao Yang 0004
ISCA1
2023 GROW: A Row-Stationary Sparse-Dense GEMM Accelerator for Memory-Efficient Graph Convolutional Neural Networks
abstract
Graph convolutional neural networks (GCNs) have emerged as a key technology in various application domains where the input data is relational. A unique property of GCNs is that its two primary execution stages, aggregation and combination, exhibit drastically different dataflows. Consequently, prior GCN accelerators tackle this research space by casting the aggregation and combination stages as a series of sparse-dense matrix multiplication. However, prior work frequently suffers from inefficient data movements, leaving significant performance left on the table. We present GROW, a GCN accelerator based on Gustavson’s algorithm to architect a row-wise product based sparse-dense GEMM accelerator. GROW co-designs the software/ hardware that strikes a balance in locality and parallelism for GCNs, reducing the average memory traffic by 2×, and achieving an average 2.8× and 2.3× improvement in performance and energy-efficiency, respectively.
Ranggi Hwang, Minhoo Kang, Dongyun Kam, Youngjoo Lee 0002, Minsoo Rhu
HPCA1
2022 DiVa: An Accelerator for Differentially Private Machine Learning
abstract
The widespread deployment of machine learning (ML) is raising serious concerns on protecting the privacy of users who contributed to the collection of training data. Differential privacy (DP) is rapidly gaining momentum in the industry as a practical standard for privacy protection. Despite DP’s importance, however, little has been explored within the computer systems community regarding the implication of this emerging ML algorithm on system designs. In this work, we conduct a detailed workload characterization on a state-of-the-art differentially private ML training algorithm named DPSGD. We uncover several unique properties of DP-SGD (e.g., its high memory capacity and computation requirements vs. non-private ML), root-causing its key bottlenecks. Based on our analysis, we propose an accelerator for differentially private ML named DiVa, which provides a significant improvement in compute utilization, leading to 2.6× higher energy-efficiency vs. conventional systolic arrays.
Beomsik Park, Ranggi Hwang, Dongho Yoon, Yoonhyuk Choi, Minsoo Rhu
MICRO2
2020 Centaur: A Chiplet-based, Hybrid Sparse-Dense Accelerator for Personalized Recommendations
abstract
Personalized recommendations are the backbone machine learning (ML) algorithm that powers several important application domains (e.g., ads, e-commerce, etc) serviced from cloud datacenters. Sparse embedding layers are a crucial building block in designing recommendations yet little attention has been paid in properly accelerating this important ML algorithm. This paper first provides a detailed workload characterization on personalized recommendations and identifies two significant performance limiters: memory-intensive embedding layers and compute-intensive multi-layer perceptron (MLP) layers. We then present Centaur, a chiplet-based hybrid sparse-dense accelerator that addresses both the memory throughput challenges of embedding layers and the compute limitations of MLP layers. We implement and demonstrate our proposal on an Intel HARPv2, a package-integrated CPU+FPGA device, which shows a 1.7-17.2× performance speedup and 1.7-19.5× energy efficiency improvement than conventional approaches.
Ranggi Hwang, Youngeun Kwon, Minsoo Rhu
ISCA1