Non-volatile memory (NVM) is a new storage technology that combines the performance and byte addressability of DRAM with the persistence of traditional storage devices like flash (SSD). While these properties make NVM highly promising, it is not yet clear how to best integrate NVM into the storage layer of modern database systems. Two system designs have been proposed. The first is to use NVM exclusively, i.e., to store all data and index structures on it. However, because NVM has a higher latency than DRAM, this design can be less efficient than main-memory database systems. For this reason, the second approach uses a page-based DRAM cache in front of NVM. This approach, however, does not utilize the byte addressability of NVM and, as a result, accessing an uncached tuple on NVM requires retrieving an entire page.

Analog IP cores exhibit a multivariate response to dynamic variations of an operation environment, that are typically represented by power and substrate voltage changes. A testbench provides a silicon area to embed and diagnose custom IP cores with power delivery and substrate networks, where the area is surrounded by on-chip precision waveform capturing and configurable power and substrate noise generation circuits. The coefficients of noise propagation and noise coupling are quantitatively derived for fabless IP cores processed in a target technology, that will be further linked with EDA tooling for the successful adoption of such IP cores in SoC integration.

An on-chip waveform capturing technique demonstrates 8.5 ENOB and 62.7 dB SFDR at 200 Ms/s for analog signals with 25-MHz bandwidth and 2.5 V rail-to-rail offset DC level, suitable for testing and self diagnosis of a mixed-signal chip. The area of 0.004mm2in a 90 nm CMOS chip is only required for the integration of probing front end circuitry, with the help of an efficient discretization algorithm on a digital data processing chain involving on-chip logic paths, an off-chip 8 bit micro controller, and PC. Waveform acquisition at the system throughput of 1.9 transaction/point is achieved, by minimizing the number of slow-speed transactions between external measurement equipments and PC.