Graph neural networks (GNNs) are increasingly used in edge and mobile applications, but the large memory requirements of GNN hardware limit their deployment on resource-constrained devices. A common solution is graph partitioning, which splits large graphs into smaller partitions that fit into on-chip memory. However, this creates halo nodes—duplicated nodes across partitions—that lead to frequent and redundant accesses to external DRAM. This paper presents SiGNoR, an efficient graph partitioning approach that introduces three hardware-friendly techniques to reduce memory access with negligible accuracy loss. First, 1) similarity-based node reuse reduces redundant DRAM access of halo nodes by leveraging only local nodes within the same partition. To further improve the impact of the halo-to-local node replacement on GNN accuracy, 2) multiphase graph partitioning is proposed to refine partition boundaries by iteratively identifying and modeling its effects. Finally, 3) partition-wise block floating-point is presented for an energy efficient GNN accelerator hardware. The proposed partition-wise block floating-point shares a single exponent across all node features within each partition, reducing memory usage. Experimental results show that SiGNoR reduces average DRAM traffic of 44.5% with negligible accuracy degradation for GNNs across six real-world graph datasets. The GNN accelerator also improves energy efficiency by up to 2.6× compared to previous GNN hardware.

In this paper, we present an energy-efficient SNN architecture, which can seamlessly run deep spiking neural networks (SNNs) with improved accuracy. First, we propose a conversion aware training (CAT) to reduce ANN-to-SNN conversion loss without hardware implementation overhead. In the proposed CAT, the activation function developed for simulating SNN during ANN training, is efficiently exploited to reduce the data representation error after conversion. Based on the CAT technique, we also present a time-to-first-spike coding that allows lightweight logarithmic computation by utilizing spike time information. The SNN processor design that supports the proposed techniques has been implemented using 28nm CMOS process. The processor achieves the top-1 accuracies of 91.7%, 67.9% and 57.4% with inference energy of 486.7uJ, 503.6uJ, and 1426uJ to process CIFAR-10, CIFAR-100, and Tiny-ImageNet, respectively, when running VGG-16 with 5bit logarithmic weights.

In this paper, we present a novel spike prediction technique based spiking neural network (SNN) architecture, which can provide low cost on-chip learning based on the sparse direct feedback alignment (DFA). First, in order to reduce the repetitive synaptic operations in feedforward operations, a spike prediction technique is proposed, where the output spikes of active and inactive neurons are predicted by tracing the membrane potential changes. The proposed spike prediction achieves 63.84% reduction of the synaptic operations, and it can be efficiently exploited in the training as well as inference process. In addition, the number of weight updates in backward operations has been reduced by applying sparse DFA. In the sparse DFA, the synaptic weight updates are computed using the sparse feedback connections and the output error that is sparse as well. As a result, the number of weight updates in the training process has been reduced to 65.17%. The SNN processor with the proposed spike prediction technique and the sparse DFA has been implemented using 65nm CMOS process. The implementation results show that the SNN processor achieves the training energy savings of 52.16% with 0.3% accuracy degradation in MNIST dataset. It also consumes 1.18 uJ/image and 1.34 uJ/image for inference and training, respectively, with 97.46% accuracy on MNIST dataset.