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Hussain Khajanchi

dblp:274/5830 · DBLP profile ↗
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1ranked-venue papers
0as first author
1since 2021 · last 2025
0009-0007-3969-1047ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 since 2021Software engineering, systems software and programming languages · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 44% Processor architecture and microarchitecture · 44% Energy-efficient computing · 13%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware/software co-design
compiler-architecture co-design
0.912025
Saving Energy with Per-Variable Bitwidth Speculation · ASPLOS (2) 2025
Processor architecture and microarchitecture
speculative execution
0.912025
Saving Energy with Per-Variable Bitwidth Speculation · ASPLOS (2) 2025
Energy-efficient computing
energy-constrained computing
0.312025
Saving Energy with Per-Variable Bitwidth Speculation · ASPLOS (2) 2025

Methods — techniques the papers use, named apart from their topics

hardware speculation · 0.9compiler optimization · 0.9
YearPublicationVenuePosition
2025 Saving Energy with Per-Variable Bitwidth Speculation
abstract
Tiny devices have become ubiquitous in people's daily lives. Their applications dictate tight energy budgets, but also require reasonable performance to meet user expectations. To this end, the hardware of tiny devices has been highly optimized, making further optimizations difficult. In this work, we identify a missed opportunity: the bitwidth selection of program variables. Today's compilers directly translate the bitwidth specified in the source code to the binary. However, we observe that most variables do not utilize the full bitwidth specified in the source code for the majority of execution. To leverage this opportunity, we propose BitSpec : a system that performs fine-grained speculation on the bitwidth of program variables. BitSpec is implemented as a compiler-architecture co-design, where the compiler transparently reduces the bitwidth of program variables to their expected needs and the hardware monitors speculative variables, reporting misspeculation to the software, which re-executes at the original bitwidth, ensuring correctness. BitSpec reduces energy consumption by 9.9% on average, up to 28.2% .
Tommy McMichen, David Dlott, Panitan Wongse-ammat, Nathan Greiner, Hussain Khajanchi, Russ Joseph, Simone Campanoni
ASPLOS (2)5