Demo Data from SIGIR 2026 / reviewers in the wild / expert
Brandon D'Agostino
dblp:276/1012
· DBLP profile ↗
2ranked-venue papers
0as first author
1since 2021 · last 2022
0000-0001-5514-072XORCID · reported
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Network and information security
1 paper |
Hardware security and side channels · 100% | |
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Processor architecture and microarchitecture · 100% |
Topics — the 4 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Hardware security and side channels › trusted execution environments
secure enclaves |
0.4 | 1 | 2020 | OPTIMUS: A Security-Centric Dynamic Hardware Partitioning Scheme for Processors that Prevent Microarchitecture State Attacks · IEEE Trans. Computers 2020 |
Hardware security and side channels
trusted execution environments |
0.4 | 1 | 2020 | OPTIMUS: A Security-Centric Dynamic Hardware Partitioning Scheme for Processors that Prevent Microarchitecture State Attacks · IEEE Trans. Computers 2020 |
Processor architecture and microarchitecture
hardware isolation |
0.4 | 1 | 2020 | OPTIMUS: A Security-Centric Dynamic Hardware Partitioning Scheme for Processors that Prevent Microarchitecture State Attacks · IEEE Trans. Computers 2020 |
Processor architecture and microarchitecture › hardware-assisted security
secure processor architecture |
0.4 | 1 | 2020 | OPTIMUS: A Security-Centric Dynamic Hardware Partitioning Scheme for Processors that Prevent Microarchitecture State Attacks · IEEE Trans. Computers 2020 |
Methods — techniques the papers use, named apart from their topics
dynamic hardware partitioning · 0.9
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2022 | Amber: Coarse-Grained Reconfigurable Array-Based SoC for Dense Linear Algebra AccelerationabstractDedicated hardware accelerators popular for imaging, vision, and machine learning (ML) applications Kathleen Feng, Alex Carsello, Taeyoung Kong, Kalhan Koul, Qiaoyi Liu, Jackson Melchert, Gedeon Nyengele, Maxwell Strange, Keyi Zhang, Ankita Nayak, Jeff Setter, James Thomas 0003, Kavya Sreedhar, Nikhil Bhagdikar, Zachary A. Myers, Brandon D'Agostino, Pranil Joshi, Stephen Richardson, Rick Bahr, Christopher Torng, Mark Horowitz, Priyanka Raina |
HCS | 17 |
| 2020 | OPTIMUS: A Security-Centric Dynamic Hardware Partitioning Scheme for Processors that Prevent Microarchitecture State AttacksabstractHardware virtualization allows multiple security-critical and ordinary (insecure) processes to co-execute on a processor. These processes temporally share hardware resources and endure numerous security threats on the microarchitecture state. State-of-the-art secure processor architectures, such as MI6 and IRONHIDE enable capabilities to execute security-critical processes in hardware isolated enclaves utilizing thestrong isolationsecurity primitive. The MI6 processor purges small state resources on each enclave entry/exit and statically partitions the last-level cache and DRAM regions to ensure strong isolation. IRONHIDE takes a spatial approach and creates two isolated clusters of cores in a multicore processor to ensure strong isolation for processes executing in the enclave cluster. Both architectures observe performance degradation due to static partitioning of shared hardware resources. OPTIMUS proposes asecurity-centricdynamic hardware resource partitioning scheme that operates entirely at runtime and ensures strong isolation. It enablesdeterministicresource allocations at the application level granularity, and limits the number of hardware reconfigurations to ensureboundedinformation leakage via the timing and termination channels. The dynamic hardware resource partitioning capability of OPTIMUS is shown to co-optimize performance and security for the MI6 and IRONHIDE architectures. Hamza Omar, Brandon D'Agostino, Omer Khan |
IEEE Trans. Computers | 2 |