Demo Data from SIGIR 2026 / reviewers in the wild / expert
Hong H. Jiang
dblp:277/5844
· DBLP profile ↗
1ranked-venue papers
0as first author
1since 2021 · last 2024
0009-0005-6944-3883ORCID · reported
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
High-performance computing · 40% Reconfigurable computing and FPGAs · 20% Hardware accelerators and domain-specific architectures · 20% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Reconfigurable computing and FPGAs
FPGA accelerator |
0.8 | 1 | 2024 | POPA: Expressing High and Portable Performance across Spatial and Vector Architectures for Tensor Computations · FPGA 2024 |
Parallel and multicore computing
parallel programming models |
0.8 | 1 | 2024 | POPA: Expressing High and Portable Performance across Spatial and Vector Architectures for Tensor Computations · FPGA 2024 |
High-performance computing › performance engineering
performance portability |
0.8 | 1 | 2024 | POPA: Expressing High and Portable Performance across Spatial and Vector Architectures for Tensor Computations · FPGA 2024 |
Hardware accelerators and domain-specific architectures
tensor accelerator |
0.8 | 1 | 2024 | POPA: Expressing High and Portable Performance across Spatial and Vector Architectures for Tensor Computations · FPGA 2024 |
High-performance computing
tensor computation |
0.8 | 1 | 2024 | POPA: Expressing High and Portable Performance across Spatial and Vector Architectures for Tensor Computations · FPGA 2024 |
Methods — techniques the papers use, named apart from their topics
vector architecture · 0.8spatial architecture · 0.8
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2024 | POPA: Expressing High and Portable Performance across Spatial and Vector Architectures for Tensor ComputationsabstractThis paper aims at high and portable performance for tensor computations across spatial (e.g., FPGAs) and vector architectures (e.g., GPUs). The state-of-the-art usually address performance portability across vector architectures (CPUs and GPUs). However, they either miss FPGAs or do not achieve high performance. Without a common architectural abstraction, they program and optimize spatial and vector devices separately, causing low portability. Xiaochen Hao, Hongbo Rong, Mingzhe Zhang 0002, Ce Sun 0001, Hong H. Jiang, Yun Liang 0001 |
FPGA | 5 |