3-D NAND flash memory with vertically stacked layers has been widely applied benefiting from its large capacities and high performances. Recently, a novel open block operation scheme was proposed for further improvements of the utilization efficiency in large capacity blocks. In this article, reliability issues of the open block operation in 3-D charge-trap (CT) NAND flash memory are studied by focusing on the high raw bit error rates (RBERs) in the last programmed word-line (WL), which is named as the edge WL (EWL). By systematical characterizations, it is concluded that high RBER in the EWL originates from lateral charge migration (LCM) due to the special structure of 3-D CT NAND flash. To suppress the RBER in EWL, we propose the extra read (ER) and extra program (EP) schemes to compensate for the charge loss from LCM. The experimental results show that the RBER of EWL can be reduced by an average of 59.8% and 86.5% after adopting ER and EP schemes, respectively. Furthermore, for the highly reliable open block, we design a targeted low-density parity-check (LDPC) operation process to enhance the correction capability. By using these two methods, experimental results show that the error correction capabilities of the LDPC hard decoding are increased by 1.92 and 4.76 times, respectively.

3-D NAND flash memory has been attracting much attention owing to its ultrahigh storage density and low bit cost, and it has been widely applied in data centers and mobiles. 3-D triple-level-cell (TLC) NAND flash memory can achieve much larger storage capacity by storing 3 bits in each cell. However, the data reliability issues induced by data retention (DR) and read disturb (RD) greatly limit 3-D TLC NAND applications in hot data storage where the stored data are frequently accessed and RD is more serious. In this article, we first systematically study the retention correlated RD (RCRD) errors in 3-D charge trap (CT) TLC NAND flash memory under various conditions. Error characteristics and underlying mechanisms much different from 2-D NAND flash memory are observed: 1) for RCRD with short retention-after data program, error bits increase due to the negative-shift of program states and 2) for RCRD with long retention-after retention 12 h, error bits can be partially recovered on the contrary due to the charge compensation. We propose schemes of precharge the storage layer (PCSL) and thermally stabilize the storage layer (TSSL) to improve the reliability of 3-D NAND flash memory. By using these two methods, experimental results show that raw bit error rates (RBERs) can be significantly reduced by 30% and 20%, respectively.