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Longze Wang

dblp:279/7698 · DBLP profile ↗
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2ranked-venue papers
1as first author
2since 2021 · last 2026
0009-0007-6276-2720ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 first-author · 2 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Electronic design automation · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › timing analysis
static timing analysis
1.822026
ASAP: Accelerating Corner-Based Timing Analysis With Bayesian Active Self-Attention Neural Process · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2026
Multicorner Timing Analysis Acceleration for Iterative Physical Design of ICs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2024
Electronic design automation
timing analysis
1.822026
ASAP: Accelerating Corner-Based Timing Analysis With Bayesian Active Self-Attention Neural Process · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2026
Multicorner Timing Analysis Acceleration for Iterative Physical Design of ICs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2024
Electronic design automation
physical design
0.812024
Multicorner Timing Analysis Acceleration for Iterative Physical Design of ICs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2024

Methods — techniques the papers use, named apart from their topics

self-attention · 1.0bayesian neural process · 1.0active learning · 1.0transfer learning · 0.8kernel trick · 0.8generalized linear model · 0.8bayesian decision strategy · 0.8
YearPublicationVenuePosition
2026 ASAP: Accelerating Corner-Based Timing Analysis With Bayesian Active Self-Attention Neural Process
abstract
With the advancement of modern nanoscale technology nodes, Static Timing Analysis (STA) has become an indispensable technique for ensuring circuit reliability and performance across diverse process conditions. However, traditional STA methods scale poorly to the explosion of process corners in the nanoscale fabrication technology. Despite some seminal works in using AI to accelerate such processes, they either lack reliability or stability. To this end, we introduce ASAP, a novel approach addressing this challenge by combining both the latest deep learning methods and the classical Bayesian models to deliver scalable and accurate predictions with a self-calibration strategy to ensure reliability. Technically, the ASAP novelly integrates self-attention to help identify and prioritize crucial features under various input conditions and employs Neural Process to make confidence-based predictions for the final timing results. Furthermore, ASAP is equipped with Active Learning for self-refinement and self-correction. Experimental evaluations on benchmark circuits demonstrate that our method surpasses state-of-the-art work in STA accuracy by 18% in terms of prediction accuracy.
Longze Wang, Wei W. Xing, Zhelong Wang, Christos P. Sotiriou, Nikolaos Sketopoulos, Ning Xu 0006, Yuanqing Cheng
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1
2024 Multicorner Timing Analysis Acceleration for Iterative Physical Design of ICs
abstract
We propose a multi-corner multi-stage timing analysis prediction framework using a generalized linear model with latent features. We then further improve such methods using kernel trick extension, transfer learning with knowledge from previous designs, and multi-output feature engineering to deliver state-of-the-art (SOTA) prediction accuracy with very limited training data. Most importantly, our method is equipped with a Bayesian decision strategy to deliver reliable predictions with accuracy close to 100%, pushing the frontier of the machine-learning-based STA for practical implementation in the industry environment, where reliability is highly desired. Experimental results show that the accuracy of our proposed method outperforms the SOTA competitors by up to 4x and can improve prediction accuracy to 100% with little extra STA executions.
Wei W. Xing, Longze Wang, Zhelong Wang, Zhaoyu Shi, Ning Xu 0006, Yuanqing Cheng, Weisheng Zhao 0001
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.2