Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page
Demo Data from SIGIR 2026 / reviewers in the wild / expert

Brent H. Pease

dblp:28/1030 · DBLP profile ↗
← Back
1ranked-venue papers
0as first author
0since 2021 · last 1992
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1Software engineering, systems software and programming languages · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Processor architecture and microarchitecture · 56% Parallel and multicore computing · 36% Memory systems · 8%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Parallel and multicore computing › multiprocessor system
distributed-memory multiprocessor		 0.011992
Seamless - a latency-tolerant RISC-based multiprocessor architecture · ISCA 1992
Processor architecture and microarchitecture
multiprocessor architecture		 0.011992
Seamless - a latency-tolerant RISC-based multiprocessor architecture · ISCA 1992
Processor architecture and microarchitecture › instruction set architecture › RISC
RISC processor		 0.011992
Seamless - a latency-tolerant RISC-based multiprocessor architecture · ISCA 1992
Memory systems
data locality		 0.011992
Seamless - a latency-tolerant RISC-based multiprocessor architecture · ISCA 1992
Parallel and multicore computing
programming models		 0.011992
Seamless - a latency-tolerant RISC-based multiprocessor architecture · ISCA 1992

Methods — techniques the papers use, named apart from their topics

locality manager · 0.0data movement · 0.0
YearPublicationVenuePosition
1992 Seamless - a latency-tolerant RISC-based multiprocessor architecture
abstract
The Seamless parallel system being developed at the University of Iowa ECE Department provides a method for providing latency tolerance in physically-distributed memory systems utilizing “off-the-shelf” RISC CPU's without incurring the overhead of multithreading. Seamless encompasses an evolutionary new programming model emphasizing data locality that views communication as data movement rather than message passing I/O. A hardware Locality Manager is added to each processing element to perform this data movement concurrently with computation.
Samuel A. Fineberg, Thomas L. Casavant, Brent H. Pease
 ISCA3