This article presents a fully dynamic latched comparator with a high-gain three-stage configuration and an extra parallel feed-forward path, able to achieve a delay of 26.8 ps and a data rate of 13.5 Gb/s with less than 10−12 BER for a 5$\text{m}\text {V}_{\text {pp}}$differential input ($\Delta V_{\textrm {I}}$) at 0.5 V common-mode ($V_{\textrm {CM}}$) and 1V supply ($V_{\textrm {DD}}$). Additionally, the reduced-stacking cascaded triple-latch arrangement enables a$V_{\textrm {DD}}$. The comparator is analyzed and compared against two prior art circuits by means of derived delay and noise expressions, serving as design guidelines. The prototype comparator and its prior art are fabricated in 28 nm bulk CMOS, with delay, input-referred noise, energy/comparison, and area measurements highlighting the benefits and trade-offs of the proposed solution.

This paper proposes a novel integrated oscillator topology based on a transmission line. The frequency is extracted from the delay of the transmission line, which is intrinsically independent of temperature and supply variations. The architecture for the oscillator, guidelines for the design of the transmission line as well as the different building blocks are presented. The architecture is based on a phase-locked loop topology. The transmission line used has a 509 ps delay, an area of 2.26 mm2and a 4.38 dB power loss. The effect of process variations on the transmission line is extensively investigated. A digital driver using CMOS inverters and an analog driver based on an OTA are proposed. Both have a good stability over temperature. The Gilbert cell is proposed as a detector at the output of the transmission line and the corresponding design considerations are shown. Closed loop simulations show fast locking, a variation of 8.3°C between -10°C and 85°C and a variation of 3.70/00for Vdd± 10%.

This paper presents MOJITO, a system that performs structural synthesis of analog circuits, returning designs that are trustworthy by construction. The search space is defined by a set of expert-specified, trusted, hierarchically-organized analog building blocks, which are organized as a parameterized context-free grammar. The search algorithm is a multiobjective evolutionary algorithm that uses an age-layered population structure to balance exploration versus exploitation. It is validated with experiments to search across >;100 000 different one-stage and two-stage opamp topologies, returning human-competitive results. The runtime is orders of magnitude faster than open-ended systems, and unlike the other evolutionary algorithm approaches, the resulting circuits are trustworthy by construction. The approach generalizes to other problem domains which have accumulated structural domain knowledge, such as robotic structures, car assemblies, and modeling biological systems.

Voltage-controlled oscillator-based analog-to-digital converters utilizes the superior time resolution and digital processing power of time-domain signal processing. With its inherent first-order noise shaping property, very high accuracy can be obtained while reducing both area and power consumption. An all-digital VCO-based ADC scheme is presented which combines a differential configuration with digital calibration to obtain very high linearity. A coarse-fine quantization approach is used to reduce the circuit complexity compared to the traditional multi-bit quantization The phase resolution is increased using passive interpolation coupled VCOs. These techniques are illustrated with a 65 nm CMOS implementation of a 30 MHz BW 10-bit ADC, occupying only 0.023 mm2.

This paper demonstrates a system that performs multi-objective sizing across 100,000 analog circuit topologies simultaneously, with SPICE accuracy. It builds on a previous system, MOJITO, which searches through 3500 topologies defined by a hierarchically-organized set of 30 analog blocks. This paper improves MOJITO's results quality via three key extensions. First, it enlarges the block library to enable symmetrical transconductance amplifiers and more. Second, it improves initial topology diversity via optimization-based constraint satisfaction. Third, it maintains topology diversity during search via a novel multi-objective selection mechanism, dubbed TAPAS. MO-JITO+TAPAS is demonstrated on a problem with 6 objectives, returning a tradeoff holding 17438 nondominated designs. The tradeoff is comprised of 152 unique topologies that include the newly-introduced topologies. 59 designs across 12 topologies designs outperform an expert-designed reference circuit.

In digital phase-locked loop based fractional-N RF frequency synthesizers, the use of a Time-to-digital converter (TDC) as a quantized phase detector brings spurious emissions when synthesizing near-integer channel frequencies. The location of these fractional spurs is dependant on the resolution of the phase detector and the channel frequency being synthesized. In addition, spurs are also generated due to the non-uniform TDC quantization steps. This paper discusses a fast PLL simulation platform and a simulative analysis of the impact of SigmaDelta-noise cancellation on the fractional spurs.

This paper presents MOJITO-R, a tool that performs variation-aware structural synthesis of analog circuits. It returns trustworthy topologies by searching across a space of thousands of possible topologies defined by hierarchically organized analog structural building blocks. ldquoStructural homotopyrdquo conducts search at several objective-function tightening levels (numbers of process corners) simultaneously. Multiobjective evolutionary search returns sized topologies which trade off power, area, performances, andyield. An experimental validation run returned 78 643 Pareto-optimal designs, having 982 sized topologies with various specification/yield combinations. A decision tree is extracted to visualize the performance-topology relationship.

This paper presents a methodology for analog designers to maintain their insights into the relationship among performance specifications, topology choice, and sizing variables, despite those insights being constantly challenged by changing process nodes and new specs. The methodology is to take a data-mining perspective on a Pareto Optimal Set of sized analog circuit topologies, then doing: extraction of a specs-to-topology decision tree; global nonlinear sensitivity analysis on topology and sizing variables; and determining analytical expressions of performance tradeoffs. These approaches are all complementary as they answer different designer questions. Once the knowledge is extracted, it can be readily distributed to help other designers, without needing further synthesis. Results are shown for operational amplifier design on a database containing thousands of Pareto Optimal designs across five objectives.

An analog to digital conversion scheme based on an Asynchronous SigmaDelta Modulator is presented. It uses a Time-to-Digital converter to convert the continuous-time square wave signal produced by the Asynchronous SigmaDelta Modulator to a time-quantized digital signal. The original input signal is then recovered by applying a digital demodulation algorithm derived from general duty-cycle modulation theory. This technique shifts the complexity towards the digital domain and is therefore especially suited for ultra-low voltage technologies beyond 90 nm. Simulations show 13 bit accuracy for Bluetooth baseband 500 kHz with a first-order SigmaDelta modulator and a Time-to-Digital Converter with 10 ps resolution running at 12 MHz. Using a second-order feedback system to shape the quantization noise of the Time-to-Digital converter, the bandwidth can be increased to 12 MHz with 12 bit accuracy, suitable for video applications.

This paper introduces a novel receiver architecture for low-power IR-UWB receivers in the 3.75–4.25GHz band. The receiver correlates the incoming pulse with an approximated pulse template in the analog domain. The template is learnt digitally and transferred to the analog domain via a low resolution DAC. The paper presents the design of the mixing DAC that implements the downconverter, DAC and correlator which consumes only 875uW in 90nm CMOS technology. The DAC receiver topology requires 4dB less energy per incoming bit in comparison with current state-of-the-art IR-UWB receivers.

This paper presents MOJITO, a system which optimizes across thousands of analog circuit topologies simultaneously, and returns a set of sized topologies that collectively provide a performance tradeoff. MOJITO defines a space of possible topologies as a hierarchically organized combination of trusted analog building blocks. To minimize the setup burden: no topology selection rules or abstract behaviors need to be specified, and performance calculations are SPICE-based. The search algorithm is a novel multi-objective evolutionary algorithm that uses an age-layered population structure to balance exploration vs. exploitation. Results are shown for a space having 3528 one- and two-stage operational amplifier topologies.

A hierarchical synthesis methodology for analog and mixed-signal systems is presented that fully in a novel way integrates topology selection at all levels. A hierarchical system optimizer takes multiple topologies for all the building blocks at each hierarchical abstraction level, and generates optimal topology combinations using multi-objective evolutionary optimization techniques. With the presented methodology, system-level performance trade-offs can be generated where each design point contains valuable information on how the systems performances are influenced by different combinations of lower-level building block topologies. The generated system designs can contain all kinds of topology combinations as long as critical inter-block constraints are met. Different topologies can be assigned to building blocks with the same functional behavior, leading to more optimal hybrid designs than typically obtained in manual designs. In the experimental results, three different integrator topologies are used to generate an optimal system-level exploration trade-off for a complex high-speed DeltaSigma A/D modulator

This paper describes key points and experimental validation in the development of a bottom--up hierarchical, multi--objective evolutionary design methodology for analog blocks. The methodology is applied to a continuous--time ΔΣ A/D converter for WLAN applications, to generate a set of Pareto--optimal design solutions. The generated performance tradeoff offers the designer access to a set of optimal design solutions, from which the designer can choose a satisfactory design point according to the performance specifications. The presented method takes advantage of the Pareto--optimal performance solutions of the hierarchical lower--level sub--blocks to generate the overall Pareto--optimal set at system level. The way the lower--level performance tradeoffs are combined and propagated to higher hierarchical levels, is one of the major key points in the bottom--up methodology. The experimental results validate the methodology for a 7--block hierarchical decomposition of a complex high--speed ΔΣ A/D modulator for a WLAN 802.11a/b/g standard.

A third-order continuous-time DeltaSigma analog-to-digital converter is designed for the conversion of an input signal bandwidth of 10MHz. Design optimization towards minimal power consumption is demonstrated for the high-speed, low-power building blocks of the modulator. The presented converter achieves a dynamic range of 72dB and a signal-to-noise-and-distortion-ratio of 66dB. The modulator consumes 7.5mW. It is integrated in a 0.18mum standard CMOS technology and occupies an area of 1.65mm2

This paper compares different receiver architectures for UWB radio communication in the 3.1-5GHz band, targeting data rates up to 10Mbps, in terms of their BER performance and power consumption. A receiver, in which some correlations are carried out in the analog domain seems to outperform a fully digital receiver, commonly suggested for baseband UWB. This paper proves that for equal processing gain requirements the partially analog receiver consumes 7 times less power per received bit than the fully digital one.

Class E amplifiers are imposed by time-domain constraints. This makes the design of such amplifiers more difficult than other types of amplifiers. This paper presents a new method to analyze class E power amplifiers using state-space equations. A description by these equations makes it possible to find the correct initial conditions that leads to the steady-state solution of the amplifier. Furthermore, it is possible to derive the power balance of the power amplifier based on its state-space equations. The presented method has shown to be very valuable when designing switched power amplifiers. Furthermore, the method can also be applied for power amplifiers that do not fulfill the class E switching conditions.

An overview and comparison of different topologies for wireless architectures are discussed, where the main focus lies on the power consumption and possibilities towards integration and reduction of external components. Architectures with reduced number of building blocks (both internal and external) are presented where the main benefits are the low costs, both in the CMOS technology as well as the power.

The systematic design of a high-speed, high-accuracy Nyquist-rate A/D converter is proposed. The presented design methodology covers the complete flow and is supported by software tools. A generic behavioral model is used to explore the A/D converter's specifications during high-level design and exploration. The inputs to the flow are the specifications of the A/D converter and the technology process. The result is a generated layout and the corresponding extracted behavioral model. The approach has been applied to a real-life test case, where a Nyquist-rate 8-bit 200 MS/s 4-2 interpolating/averaging A/D converter was developed for a WLAN application.

The systematic design of a high-speed, high-accuracy Nyquist A/D converter is proposed The presented design methodology covers the complete flow and is supported by software tools. A generic behavioral model is used to explore the A/D converter's specifications during high-level design and exploration. The inputs are the specifications of the A/D converter and the technology process. The result is a generated layout and the corresponding extracted behavioral model. The approach has been applied to a real-life test case, where a Nyquist-rate 8-bit 200 MS/s 4-2 interpolating A/D converter was developed for a WLAN application.

This paper describes an optimization technique able to optimize a complete wireless receiver architecture in a reasonable amount of time. The optimizer alternates between spice level optimizations of simple building blocks and a full architecture optimization of the whole based on accurate models of the building blocks. The models of the building blocks are interpolated over the data points acquired in the Spice level simulations. The optimizer technique has been applied to the optimization of an architecture for a GPS receiver. The optimal design has been implemented in a standard 0.25μm CMOS process.

An upconvertor topology for low power, high bandwidth applications is presented. Using specific circuit techniques and local circuit-level optimization, the power consumption of the total system comprising an on-chip LC-type VCO, a polyphase network quadrature generator, a linear mixer block and an RF-current buffer, has been minimized.A chip has been designed and manufactured in a 0.25μm CMOS technology. The VCO oscillates between 1.68 GHz and 2 GHz. Driven by an external LO, the transmitter operates from 900 MHz up to 2 GHz. At 2 GHz, the upconvertor transmits -12 dBm into 50 ω with a linearity of more than -35 dBc for base band signals up to 33 MHz.

This paper presents a specification-driven layout-aware CMOS RF LC-oscillator design tool called CYCLONE. Circuit sizing and layout generation are integrated in the overall oscillator optimization. The tool optimizes the device sizes and also determines the optimal geometrical parameters of the on-chip inductor and automatically performs electromagnetic simulations to exactly calculate its losses during sizing. For the other devices in the oscillator circuit, being gain cell and varactor diode, it uses a technology-independent template-based layout generation approach to obtain accurate predictions of the actual layout parasitics. The device sizing of the gain cell is based on an operating-point linearized BSIM3 model of the gain cell transistors. The varactor diode is sized based on the BSIM3 source/drain diode models of the pMOS transistor. All parasitics; are incorporated in a global optimization of the complete oscillator circuit. After optimization of the circuit, the layout can be exported to a standard GDSII format for processing. The capabilities of the tool are demonstrated by several design experiments.

In this paper a layout-aware RF synthesis methodology is presented. The methodology combines the power of a differential evolution algorithm with cost function response modeling and integrated layout generation to synthesize RF Circuits efficiently, taking into account all layout parasitics during the circuit optimization. The proposed approach has successfully been applied to the design of a high-performance downconverter mixer circuit, proving the effectiveness of the implemented design methodology.

This paper presents an automated, layout-aware RF LC-oscillator design tool, called CYCLONE that delivers an accurate and optimal LC-oscillator design, from specification to layout. The tool combines the accuracy of device-level simulation and finite element analysis with the optimisation power of simulated annealing algorithms and is verified with experimental results.

This paper presents an optimization algorithm that is able to significantly increase the speed of RF circuit optimizations.The algorithm consists of a series of consecutive evolutionary optimizations of the circuit itself and of a modeled version thereof.The speed increase arises from the difference in evaluation time between the real simulation and the fit evaluation.As circuit approximation, behavioral models are used instead of polynomial expressions, allowing to put some "design knowledge" into the optimization.gaRFeeld is a tool implementing this smart evolutionary algorithm for RF circuits.Finally some experiments performed with gaRFeeld are illustrated for the optimization of a Low Noise Amplifier.

This paper presents the design trade-offs to implement an integrated CMOS quadrature oscillator based on a differential VCO and a differential-to-quadrature converting poly-phase filter. Both the traditional structure, with cascaded building blocks and the appropriate inter circuit buffers, and the merged version, without buffering, are discussed. In the latest, the excessive power consumption in the intermediate buffers is avoided. It is explained how the effect of the poly-phase filter on the phase noise performance of the VCO, can be taken into account in the design, resulting in an optimal trade-off between the overall power consumption and the phase-noise of the quadrature oscillation generator.

Since transistor mismatch directly affects the performances of a broad class of analog CMOS devices such as comparators, A/D and D/A converters, it is of the utmost importance to determine these parameters for every available CMOS technology. Nowadays, this is done by processing and evaluating a large number of especially designed test structures that have no further use. This paper presents a technique to extract the transistor mismatch parameters from the performance of a simple current-steering CMOS D/A converter.

To obtain a high resolution CMOS current-steering digital-to-analog converter, the matching behavior of the current source transistors is one of the key issues in the design. At this moment, these matching properties are taken into account by the use of time consuming and CPU intensive Monte Carlo simulations. In this paper a formula is derived that allows us to accurately describe the impact of the mismatch on the INL (integral non-linearity) yield of current-steering D/A converters without any loss of design time.

This paper presents a high-level analysis and optimization tool for the design of analog RF receiver front-ends, which takes all design parameters and all aspects of performance degradation (noise, distortion, self-mixing...) into account. The simulations are performed in the spectral domain with a behavioral model library for the RF building blocks. The tool allows to explore alternative RF receiver topologies as well as to investigate design trade-offs within each topology. By having integrated the performance analysis routine within a simulated annealing optimization loop, the tool can also perform an optimal high-level synthesis of a given topology towards a specific application. It then determines the optimal specifications for the RF building blocks such that the required receiver signal quality is met while the overall power and/or area consumption is minimized.

This paper presents the CMOS realisation of a programmable cellular neural network. An analogue programmable synapse circuit was designed that allows a large dynamic range for the template weights. Tuning circuits transform the digital values specified by the user to the corresponding analogue tuning voltages. A chip containing a 4x4 programmable CNN has been fabricated in a 2.4 /spl mu/m CMOS process.>