In recent years, there has been increasing attention on the capabilities of large-scale models, particularly in handling complex tasks that small-scale models are unable to perform. Notably, large language models (LLMs) have demonstrated ``intelligent'' abilities such as complex reasoning and abstract language comprehension, reflecting cognitive-like behaviors. However, current research on emergent abilities in large models predominantly focuses on the relationship between model performance and size, leaving a significant gap in the systematic quantitative analysis of the internal structures and mechanisms driving these emergent abilities. Drawing inspiration from neuroscience research on brain network structure and self-organization, we propose (i) a general network representation of large models, (ii) a new analytical framework — *Neuron-based Multifractal Analysis (NeuroMFA)* - for structural analysis, and (iii) a novel structure-based metric as a proxy for emergent abilities of large models. By linking structural features to the capabilities of large models, *NeuroMFA* provides a quantitative framework for analyzing emergent phenomena in large models. Our experiments show that the proposed method yields a comprehensive measure of the network's evolving heterogeneity and organization, offering theoretical foundations and a new perspective for investigating emergence in large models.

The complex calculations of the low-density parity-check (LDPC) decoder result in significant energy and hardware consumption. To solve the challenge, this brief describes a fully parallel stochastic LDPC decoder with a two-stage shared memory (TSM) variable node (VN). To enhance cost efficiency, our design incorporates a shared low-cost random number generator (RNG) for all 2160 channels. We introduce a TSM VN function, which demonstrates faster convergence and reduced hardware overhead in comparison with the existing methods. We have taped out the (2160, 1760) stochastic LDPC decoder in the 55-nm process. The measure results exhibit that the proposed design achieves a throughput of 57.6 Gb/s, an efficiency of 33.68 Gb/s/mm2, and a power efficiency of 4.86 pJ/bit, underlining superior performance in terms of decoding throughput, hardware efficiency, and energy conservation.

With the explosive growth in processing and data storage capability, computing in memory (CIM) technology is considered a feasible method to mitigate the memory wall. Re-cently, a floating-gate field-effect transistor (FGFET) technology with single-layer MoS2 channel was proposed, which can flexibly transfer the memory and logic gate by setting the corresponding voltage. In this paper, based on the new FGFETs devices, we propose a hardware-efficient reconfigurable logic-in-memory (LIM) circuit to perform neural network (NN) computing. We first represent the basic FGFET array as a matrix form. Thereby, the adders, multipliers, registers, and PE units are designed by the matrix function of the arrays. The proposed circuits can dynamically transfer the memory to computing logic online when fewer data are required to be stored. A theoretical experiment based on the VGG16 network exhibits an efficiency increase of 85.35% in the same logic area compared with the traditional method.