Demo Data from SIGIR 2026 / reviewers in the wild / expert
Akash Kothari
dblp:286/1950
· DBLP profile ↗
4ranked-venue papers
1as first author
4since 2021 · last 2025
—ORCID · conflict
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 1 first-author · 3 since 2021Software engineering, systems software and programming languages · 3 · 1 first-author · 3 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Software engineering, system software, and programming languages
4 papers |
Compilers and program optimization · 75% Program synthesis and code generation · 17% Programming languages and type systems · 5% | |
| Computer architecture, parallel and distributed computing, and storage systems
4 papers |
Hardware accelerators and domain-specific architectures · 50% GPUs and heterogeneous computing · 32% Energy-efficient computing · 18% |
Topics — the 10 heaviest of 12, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Compilers and program optimization › code generation
instruction selection |
1.6 | 2 | 2025 | MISAAL: Synthesis-Based Automatic Generation of Efficient and Retargetable Semantics-Driven Optimizations · Proc. ACM Program. Lang. 2025 Hydride: A Retargetable and Extensible Synthesis-based Compiler for Modern Hardware Architectures · ASPLOS (2) 2024 |
Compilers and program optimization
intermediate representation |
1.0 | 2 | 2025 | Hydride: A Retargetable and Extensible Synthesis-based Compiler for Modern Hardware Architectures · ASPLOS (2) 2024 HPVM-HDC: A Heterogeneous Programming System for Accelerating Hyperdimensional Computing · ISCA 2025 |
Program synthesis and code generation
rewrite rule inference |
0.9 | 1 | 2025 | MISAAL: Synthesis-Based Automatic Generation of Efficient and Retargetable Semantics-Driven Optimizations · Proc. ACM Program. Lang. 2025 |
Hardware accelerators and domain-specific architectures › neural network hardware › brain-inspired computing accelerator
hyperdimensional computing accelerator |
0.9 | 1 | 2025 | HPVM-HDC: A Heterogeneous Programming System for Accelerating Hyperdimensional Computing · ISCA 2025 |
Compilers and program optimization › compiler construction
retargetable compilation |
0.8 | 1 | 2024 | Hydride: A Retargetable and Extensible Synthesis-based Compiler for Modern Hardware Architectures · ASPLOS (2) 2024 |
Compilers and program optimization
approximate computing |
0.5 | 1 | 2021 | ApproxTuner: a compiler and runtime system for adaptive approximations · PPoPP 2021 |
Energy-efficient computing › energy-quality tradeoff
energy-accuracy tradeoff |
0.5 | 1 | 2021 | ApproxTuner: a compiler and runtime system for adaptive approximations · PPoPP 2021 |
Programming languages and type systems
domain-specific languages |
0.3 | 1 | 2025 | HPVM-HDC: A Heterogeneous Programming System for Accelerating Hyperdimensional Computing · ISCA 2025 |
Hardware accelerators and domain-specific architectures
tensor accelerator |
0.3 | 1 | 2025 | MISAAL: Synthesis-Based Automatic Generation of Efficient and Retargetable Semantics-Driven Optimizations · Proc. ACM Program. Lang. 2025 |
Hardware accelerators and domain-specific architectures
domain-specific compilers |
0.2 | 1 | 2024 | Hydride: A Retargetable and Extensible Synthesis-based Compiler for Modern Hardware Architectures · ASPLOS (2) 2024 |
Methods — techniques the papers use, named apart from their topics
term rewriting · 1.7reduction perforation · 1.7program synthesis · 1.7formal semantics · 1.7automatic binarization · 1.7synthesis-based compilation · 1.5pseudocode specification · 1.5approximation tuning · 1.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | HPVM-HDC: A Heterogeneous Programming System for Accelerating Hyperdimensional ComputingabstractHyperdimensional Computing (HDC), a technique inspired by cognitive models of computation, has been proposed as an efficient and robust alternative basis for machine learning.HDC programs are often manually written in low-level and target specific languages targeting CPUs, GPUs, and FPGAs-these codes cannot be easily retargeted onto HDC-specific accelerators.No previous programming system enables productive development of HDC programs and generates efficient code for several hardware targets.We propose a heterogeneous programming system for HDC: a novel programming language, HDC++, for writing applications using a unified programming model, including HDC-specific primitives to improve programmability, and a heterogeneous compiler, HPVM-HDC, that provides an intermediate representation for compiling HDC programs to many hardware targets.We implement two tuning optimizations, automatic binarization and reduction perforation, that exploit the error resilient nature of HDC.Our evaluation shows that HPVM-HDC generates performance-competitive code for CPUs and GPUs, achieving a geomean speed-up of 1.17x over optimized baseline CUDA implementations with a geomean * Equally contributing authors. Russel Arbore, Xavier Routh, Abdul Rafae Noor, Akash Kothari, Haichao Yang, Sumukh Pinge, Minxuan Zhou, Tajana Rosing, Vikram S. Adve |
ISCA | 4 |
| 2025 | MISAAL: Synthesis-Based Automatic Generation of Efficient and Retargetable Semantics-Driven OptimizationsabstractUsing program synthesis to select instructions for and optimize input programs is receiving increasing attention. However, existing synthesis-based compilers are faced by two major challenges that prohibit the deployment of program synthesis in production compilers: exorbitantly long synthesis times spanning several minutes and hours; and scalability issues that prevent synthesis of complex modern compute and data swizzle instructions, which have been found to maximize performance of modern tensor and stencil workloads. This paper proposes Misaal , a synthesis-based compiler that employs a novel strategy to use formal semantics of hardware instructions to automatically prune a large search space of rewrite rules for modern complex instructions in an offline stage. Misaal also proposes a novel methodology to make term-rewriting process in the online stage (at compile-time) extremely lightweight so as to enable programs to compile in seconds. Our results show that Misaal reduces compilation times by up to a geomean of 16x compared to the state-of-theart synthesis-based compiler, Hydride . Misaal also delivers competitive runtime performance against the production compiler for image processing and deep learning workloads, Halide, as well as Hydride across x86, Hexagon and ARM. Abdul Rafae Noor, Dhruv Baronia, Akash Kothari, Muchen Xu, Charith Mendis, Vikram S. Adve |
Proc. ACM Program. Lang. | 3 |
| 2024 | Hydride: A Retargetable and Extensible Synthesis-based Compiler for Modern Hardware ArchitecturesabstractAs modern hardware architectures evolve to support increasingly diverse, complex instruction sets for meeting the performance demands of modern workloads in image processing, deep learning, etc., it has become ever more crucial for compilers to provide robust support for evolution of their internal abstractions and retargetable code generation support to keep pace with emerging instruction sets. We propose Hydride, a novel approach to compiling for complex, emerging hardware architectures. Hydride uses vendor-defined pseudocode specifications of multiple hardware ISAs to automatically design retargetable instructions for AutoLLVM IR, an extensible compiler IR which consists of (formally defined) language-independent and target-independent LLVM IR instructions to compile to those ISAs, and automatically generated instruction selection passes to lower AutoLLVM IR to each of the specified hardware ISAs. Hydride also includes a code synthesizer that automatically generates code generation support for schedule-based languages, such as Halide, to optimally generate AutoLLVM IR. Our results show that Hydride is able to represent 3,557 instructions combined in x86, Hexagon, ARM architectures using only 397 AutoLLVM IR instructions, including (Intel) SSE2, SSE4, AVX, AVX2, AVX512, (Qualcomm) Hexagon HVX, and (ARM) NEON vector ISAs. We created a new Halide compiler with Hydride using only a formal semantics of Halide IR, leveraging the auto-generated AutoLLVM IR and back-ends for the three hardware architectures. Across kernels from deep learning and image processing, this compiler is able to perform just as well as the mature, production Halide compiler on Hexagon, and outperform on x86 by 8% and ARM by 3%. Hydride also outperforms the production Halide's LLVM back end by 12% on x86, 100% on HVX, and 26% on ARM across the same kernels. Akash Kothari, Abdul Rafae Noor, Muchen Xu, Hassam Uddin, Dhruv Baronia, Stefanos Baziotis, Vikram S. Adve, Charith Mendis, Sudipta Sengupta |
ASPLOS (2) | 1 |
| 2021 | ApproxTuner: a compiler and runtime system for adaptive approximationsabstractManually optimizing the tradeoffs between accuracy, performance and energy for resource-intensive applications with flexible accuracy or precision requirements is extremely difficult. We present ApproxTuner, an automatic framework for accuracy-aware optimization of tensor-based applications while requiring only high-level end-to-end quality specifications. ApproxTuner implements and manages approximations in algorithms, system software, and hardware. Hashim Sharif, Yifan Zhao 0004, Maria Kotsifakou, Akash Kothari, Benjamin Schreiber 0001, Elizabeth Wang, Yasmin Sarita, Nathan Zhao, Keyur Joshi 0001, Vikram S. Adve, Sasa Misailovic, Sarita V. Adve |
PPoPP | 4 |