Circuit fabrics composed of highly regular structures, called logic bricks, have been described recently for improving yield. An automated logic brick design flow based on a SAT formulation of the brick routing has been developed to minimize wire length and the number of vias while maintaining several design-for-manufacturability constraints. In this work, testability enhancements are imposed into a logic brick to reduce the likelihood of (i) feedback bridges to improve test and (ii) equivalent faults to improve diagnosis. This is accomplished by adding constraints to the SAT formulation of the logic brick routing that restricts certain wires from being routed in close proximity, thus making bridges between them unlikely. Application to several brick designs resulted in critical-area reductions for targeted bridges with little degradation in terms of additional wire length and via count.

Multiple-detect test sets detect single stuck line faults multiple times, and thus have a higher probability of detecting complex defects. But current definitions of what constitutes a new test for a single stuck line fault do not leverage defect locality. Recent work has proposed a new metric to capture quality of a multiple-detect test set based on the number of unique states on lines in the physical neighborhood of a targeted line. This paper presents a new ATPG strategy that uses this metric to generate higher quality multiple-detect test sets.

Defect density and defect size distributions (DDSDs) are key parameters used in IC yield loss predictions. Traditionally, memories and specialized test structures have been used to estimate these distributions. In this paper, we propose a strategy to accurately estimate DDSDs for shorts in metal layers using production IC test results

Inductive fault analysis is the process of determining which defects are likely to occur in an integrated circuit for a given manufacturing process. Although IFA provides a more accurate defect list for test than standard fault models, it typically retires a significant amount of computation time. We propose, a methodology that exploits the physical regularity of a design to reduce the computation time, required for IFA. This methodology was applied to several designs implemented in a via-programmable gate array (an example of a regular circuit fabric) and shown to provide an average speedup of 46times

A built-in self-test algorithm is developed for chemically-assembled electronic nanotechnology (CAEN) that exploits reconfigurability to achieve 100% fault coverage and nearly 100% diagnostic accuracy. This algorithm is particularly suited for regular architectures with high defect densities.

Diagnosis algorithms for integrated circuits (ICs) are typically developed and evaluated using a limited number of logic-level models of defect behaviors. However, it is well-known that real IC defects exhibit behavior well outside these models. Consequently, the utility of IC diagnosis methodologies may be uncertain. A simulation-based benchmarking strategy is developed that uses circuit-level models to describe the complex nature of real defects. Specifically, we have proposed a simple yet powerful strategy using a small circuit and a set of bounded deformations (i.e., defects) for measuring the effectiveness of diagnosis techniques. Evaluation of several simple and commercial diagnosis algorithms indicates that this form of diagnosis benchmarking is viable.