Demo Data from SIGIR 2026 / reviewers in the wild / expert
S. S. S. P. Rao
dblp:29/4772
· DBLP profile ↗
6ranked-venue papers
3as first author
0since 2021 · last 1996
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 4 · 3 first-authorGraphics, computer vision, multimedia, augmented reality and games · 2
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Electronic design automation · 40% Storage systems · 26% Performance modeling and evaluation · 26% |
Topics — the 6 heaviest of 7, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Storage systems › file systems › distributed file system
parallel file system |
0.0 | 1 | 1996 | Impact of Delays in Parallel I/O System: An Empirical Study · HPDC 1996 |
Electronic design automation › logic synthesis
datapath optimization |
0.0 | 1 | 1989 | Interface Optimization: An Algorithm for the Detection of Data Path Redundancy and Reconfigurability Towards Obtaining Minimal Bus Interfaces · IEEE Trans. Computers 1989 |
Electronic design automation
high-level synthesis |
0.0 | 1 | 1989 | Interface Optimization: An Algorithm for the Detection of Data Path Redundancy and Reconfigurability Towards Obtaining Minimal Bus Interfaces · IEEE Trans. Computers 1989 |
Electronic design automation › system-level design › communication synthesis
interface synthesis |
0.0 | 1 | 1989 | Interface Optimization: An Algorithm for the Detection of Data Path Redundancy and Reconfigurability Towards Obtaining Minimal Bus Interfaces · IEEE Trans. Computers 1989 |
Electronic design automation
logic synthesis |
0.0 | 1 | 1989 | Interface Optimization: An Algorithm for the Detection of Data Path Redundancy and Reconfigurability Towards Obtaining Minimal Bus Interfaces · IEEE Trans. Computers 1989 |
Parallel and multicore computing
multiprocessor system |
0.0 | 1 | 1996 | Impact of Delays in Parallel I/O System: An Empirical Study · HPDC 1996 |
Methods — techniques the papers use, named apart from their topics
performance modeling · 0.0empirical measurement · 0.0network flow · 0.0graph algorithms · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1996 | Impact of Delays in Parallel I/O System: An Empirical StudyabstractPerformance of I/O intensive applications on a multiprocessor system depends mostly on the variety of disk access delays encountered in the I/O system. Over the years, the improvement in disk performance has taken place more slowly than the corresponding increase in processor speeds. It is therefore necessary to model I/O delays and evaluate performance benefits of moving an application to a better multiprocessor system. We perform such an analysis by measuring I/O delays for a synthesized application that uses a parallel distributed file system. The aim of this study is to evaluate the performance benefits of better disks in a multiprocessor system. We report on how the I/O performance would be affected if an application were to run on a system which would have better disks and communication links. In this study, we show a substantial improvement in the performance of an I/O system with better disks and communication links with respect to the existing system. C. R. Venugopal, S. S. S. P. Rao |
HPDC | 2 |
| 1992 | PLX: A proposal to implement a general broadcasting facility in a distributed environment running X windows
Y. Z. Lashkari, S. S. S. P. Rao, V. Y. Mhaskar, A. C. Shelat |
Comput. Graph. | 2 |
| 1989 | Interface Optimization: An Algorithm for the Detection of Data Path Redundancy and Reconfigurability Towards Obtaining Minimal Bus InterfacesabstractInterconnections of submodules of digital systems are normally achieved directly by connecting them to a bus through driver/receiver links. The authors present algorithms for the implementation of data transfer requirements of a system through indirect paths. A formal procedure for identifying the possible candidates for indirect path realization is reported. A procedure is proposed for optimizing the interconnections in a digital system using both indirect and direct paths. It serves as an effective design tool in LSI/VLSI realization of digital systems.> S. S. S. P. Rao, J. R. Isaac |
IEEE Trans. Computers | 1 |
| 1987 | GKS implementation: A case study
Shishir Pardikar, Mahesh Vaidya, S. S. S. P. Rao |
Comput. Graph. | 3 |
| 1985 | Micro-store width optimization through bit steering
S. S. S. P. Rao, J. R. Isaac |
Microprocessing and Microprogramming | 1 |
| 1984 | Micro-store optimization based on micro-operation utilisation profile
S. S. S. P. Rao, V. Ramesh |
Microprocessing and Microprogramming | 1 |