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Ayman Abouelwafa

dblp:291/6028 · DBLP profile ↗
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3ranked-venue papers
0as first author
2since 2021 · last 2023
0000-0002-4618-2618ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Memory systems · 80% Hardware accelerators and domain-specific architectures · 20%
Software engineering, system software, and programming languages
1 paper
Operating systems · 100%

Topics — the 6 heaviest of 7, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems › memory management › virtual memory
address translation
0.612022
Reducing Minor Page Fault Overheads through Enhanced Page Walker · ACM Trans. Archit. Code Optim. 2022
Memory systems › memory management › virtual memory
page fault handling
0.612022
Reducing Minor Page Fault Overheads through Enhanced Page Walker · ACM Trans. Archit. Code Optim. 2022
Memory systems › memory management › virtual memory › address translation
TLB
0.612022
Reducing Minor Page Fault Overheads through Enhanced Page Walker · ACM Trans. Archit. Code Optim. 2022
Memory systems › memory management
virtual memory
0.612022
Reducing Minor Page Fault Overheads through Enhanced Page Walker · ACM Trans. Archit. Code Optim. 2022
Operating systems › resource management
memory management
0.212022
Reducing Minor Page Fault Overheads through Enhanced Page Walker · ACM Trans. Archit. Code Optim. 2022
Operating systems › resource management › memory management
page allocation
0.212022
Reducing Minor Page Fault Overheads through Enhanced Page Walker · ACM Trans. Archit. Code Optim. 2022

Methods — techniques the papers use, named apart from their topics

hardware-software co-design · 1.1gem5 simulation · 1.1
YearPublicationVenuePosition
2023 K8sES: Optimizing Kubernetes with Enhanced Storage Service-Level Objectives
abstract
Kubernetes (k8s) is a system for managing containerized applications across multiple hosts. It offers automatic deployment, maintenance, scaling, and resource management for applications. Applications in k8s usually have different storage requirements in the form of service-level objectives (SLOs). However, the current k8s storage management has several limitations which cause explicit performance and cost overhead. K8s administrators have to configure storage in advance manually, and users must know configurations and capabilities of provided storage. Users' storage SLOs can be easily violated in k8s.In this paper, we design and implement k8s Enhanced Storage (k8sES) which efficiently supports applications with various storage SLOs along with all other requirements in the Kubernetes environment. We design and incorporate storage scheduling as part of the node scheduling process in k8s. Applications will be scheduled onto the correct nodes and storage without intervention from either users or administrators. Proper storage resources will be dynamically carved based on users' storage SLOs. In addition, we provide a tool to monitor the I/O activities of both applications and storage devices in k8sES. The evaluation shows that k8sES can better meet users' storage SLOs along with other requirements. Also, k8sES can achieve higher resource utilization efficiency with overhead similar to that of the current k8s.
Hao Wen 0001, Zhichao Cao 0002, Bingzhe Li, David Hung-Chang Du, Ayman Abouelwafa, Doug Voigt, Shiyong Liu, Jim Diehl, Fenggang Wu
ICCD5
2022 Reducing Minor Page Fault Overheads through Enhanced Page Walker
abstract
Application virtual memory footprints are growing rapidly in all systems from servers down to smartphones. To address this growing demand, system integrators are incorporating ever larger amounts of main memory, warranting rethinking of memory management. In current systems, applications produce page fault exceptions whenever they access virtual memory regions that are not backed by a physical page. As application memory footprints grow, they induce more and more minor page faults. Handling of each minor page fault can take a few thousands of CPU cycles and blocks the application till the OS kernel finds a free physical frame. These page faults can be detrimental to the performance when their frequency of occurrence is high and spread across application runtime. Specifically, lazy allocation-induced minor page faults are increasingly impacting application performance. Our evaluation of several workloads indicates an overhead due to minor page faults as high as 29% of execution time. In this article, we propose to mitigate this problem through a hardware, software co-design approach. Specifically, we first propose to parallelize portions of the kernel page allocation to run ahead of fault time in a separate thread. Then we propose the Minor Fault Offload Engine (MFOE), a per-core hardware accelerator for minor fault handling. MFOE is equipped with a pre-allocated page frame table that it uses to service a page fault. On a page fault, MFOE quickly picks a pre-allocated page frame from this table, makes an entry for it in the TLB, and updates the page table entry to satisfy the page fault. The pre-allocation frame tables are periodically refreshed by a background kernel thread, which also updates the data structures in the kernel to account for the handled page faults. We evaluate this system in the gem5 architectural simulator with a modified Linux kernel running on top of simulated hardware containing the MFOE accelerator. Our results show that MFOE improves the average critical path fault handling latency by 33× and tail critical path latency by 51×. Among the evaluated applications, we observed an improvement of runtime by an average of 6.6%.
Chandrahas Tirumalasetty, Chih-Chieh Chou, A. L. Narasimha Reddy, Paul Gratz, Ayman Abouelwafa
ACM Trans. Archit. Code Optim.5
2020 FussyCache: A Caching Mechanism for Emerging Storage Hierarchies
abstract
In this paper, we propose a novel caching mechanism, called FussyCache, that differs from the traditional DRAM caching mechanisms that automatically cache a data block when it is requested. Instead, FussyCache evaluates each requested data block for its caching eligibility, and reads ineligible blocks directly from the device each time. We show that the Fussy-Cache performs substantially better than the traditional caching algorithms and its performance increases with the storage device speed. In particular, for the first generation Intel Optane based storage, FussyCache provides 25-30% reduction in the average access latency as compared to the native caching mechanism such as plain LRU. We also observe close to 15-20% improvement in performance even for a mainstream TLC SSD. Furthermore, the FussyCache design includes two mechanisms that allow for its easy deployment in any environment: (a) a self-monitoring stage that reverts it to a normal LRU when partial caching is not beneficial, and (b) a training phase that automatically tunes the configurable parameters for the deployment environment.
Jit Gupta, Krishna Kant 0001, Ayman Abouelwafa
CloudCom3