Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page

Behnam Omidi

dblp:292/5439 · DBLP profile ↗
← Back
7ranked-venue papers
1as first author
7since 2021 · last 2026
0000-0002-6724-2093ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 1 first-author · 3 since 2021Security and privacy · 3 · 3 since 2021Computer networks · 1 · 1 since 2021Software engineering, systems software and programming languages · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
4 papers
Cloud and datacenter computing · 74% Processor architecture and microarchitecture · 20% Reconfigurable computing and FPGAs · 6%
Network and information security
5 papers
Hardware security and side channels · 50% Security and privacy of machine learning · 30% Systems and software security · 20%

Topics — the 8 heaviest of 10, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Cloud and datacenter computing › cloud security
co-location attacks
1.622026
Bit of a Close Talker: A Practical Guide to Serverless Cloud Co-Location Attacks · NDSS 2026
Repttack: Exploiting Cloud Schedulers to Guide Co-Location Attacks · NDSS 2022
Cloud and datacenter computing
serverless computing
1.012026
Bit of a Close Talker: A Practical Guide to Serverless Cloud Co-Location Attacks · NDSS 2026
Hardware security and side channels › side-channel countermeasures
microarchitectural side-channel defense
0.912025
Data Oblivious CPU: Microarchitectural Side-channel Leakage-Resilient Processor · DAC 2025
Processor architecture and microarchitecture › front-end
instruction decoding
0.912025
Data Oblivious CPU: Microarchitectural Side-channel Leakage-Resilient Processor · DAC 2025
Security and privacy of machine learning › model intellectual property protection › model ownership verification
model fingerprinting
0.812024
Architectural Whispers: Robust Machine Learning Models Fingerprinting via Frequency Throttling Side-Channels · DAC 2024
Cloud and datacenter computing
cloud security
0.712023
HeteroScore: Evaluating and Mitigating Cloud Security Threats Brought by Heterogeneity · NDSS 2023
Hardware security and side channels
side-channel attack
0.422024
Architectural Whispers: Robust Machine Learning Models Fingerprinting via Frequency Throttling Side-Channels · DAC 2024
Repttack: Exploiting Cloud Schedulers to Guide Co-Location Attacks · NDSS 2022
Systems and software security
cloud security
0.312026
Bit of a Close Talker: A Practical Guide to Serverless Cloud Co-Location Attacks · NDSS 2026

Methods — techniques the papers use, named apart from their topics

dynamic instruction decoding · 1.7FPGA prototyping · 1.7heterogeneity analysis · 1.3scheduler exploitation · 1.1time-series classification · 0.8power side-channel analysis · 0.8
YearPublicationVenuePosition
2026 Bit of a Close Talker: A Practical Guide to Serverless Cloud Co-Location Attacks
Najmeh Nazari, Behnam Omidi, Setareh Rafatirad, Khaled N. Khasawneh, Houman Homayoun, Chongzhou Fang
NDSS3
2025 Data Oblivious CPU: Microarchitectural Side-channel Leakage-Resilient Processor
abstract
Mitigating microarchitectural side channels remains a central challenge in hardware security. Despite substantial research efforts, current defenses are often narrowly tailored to specific vulnerabilities, leaving systems exposed to a broader spectrum of microarchitectural side-channel attacks. In this paper, we propose a generic approach to mitigate side-channel attacks with minimal architectural changes. Unlike traditional approaches that focus on mitigating specific side channels, we propose a dynamic strategy that alters the decoding of the instructions into secure (side-channel resilient) or performance versions of the instructions, based on the data it is processing. Specifically, to minimize performance overhead, decoding to a secure version is selectively applied only when sensitive data are being processed, ensuring optimal performance for instructions operating on non-sensitive data.To evaluate our approach, we implement it on the RISC-V out-of-order BOOM processor. Our results demonstrate that the mechanism increases the utilization of FPGA resources by only 2% compared to the original design. Furthermore, it imposes 0% performance overhead for unprotected applications, while maintaining overhead between up to 25% for security-critical workloads. This work represents a scalable and efficient solution for defending against micro-architectural side-channel attacks without compromising system performance.
Behnam Omidi, Ihsen Alouani, Khaled N. Khasawneh
DAC1
2025 Assessing and Mitigating Heterogeneity-Driven Security Threats in the Cloud
abstract
Cloud computing has become crucial for the commercial world due to its computational capacity, storage capabilities, scalability, software integration, and billing convenience. Initially, clouds were relatively homogeneous, but now diverse machine configurations in heterogeneous clouds are recognized for their improved application performance and energy efficiency. This shift is driven by the integration of various hardware to accommodate diverse user applications. However, alongside these advancements, security threats like micro-architectural attacks are increasing concerns for cloud providers and users. Studies like Repttack and Cloak & Co-locate highlight the vulnerability of heterogeneous clouds to co-location attacks, where attacker and victim instances are placed together. The ease of these attacks isn’t solely linked to heterogeneity but also correlates with how heterogeneous the target systems are. Despite this, no numerical metrics exist to quantify cloud heterogeneity. This article introduces the Heterogeneity Score (HeteroScore) to evaluate server setups and instances. HeteroScore significantly correlates with co-location attack security. The article also proposes strategies to balance diversity and security. This study pioneers the quantitative analysis connecting cloud heterogeneity and infrastructure security.
Chongzhou Fang, Najmeh Nazari, Behnam Omidi, Han Wang 0020, Aditya Puri, Manish Arora, Setareh Rafatirad, Houman Homayoun, Khaled N. Khasawneh
ACM Trans. Internet Techn.3
2024 Architectural Whispers: Robust Machine Learning Models Fingerprinting via Frequency Throttling Side-Channels
abstract
Machine Learning (ML) security practices include hiding ML model architectures to protect intellectual property and prevent attacks. We introduce a novel fingerprinting attack using frequency throttling-based Side-Channel Attack (SCA) to detect an ML model's architecture family by converting power side-channel data into timing variations. This method involves using adversary kernels and a time series ML classifier to discern the architecture from execution time patterns during model operation. We achieved up to 96% accuracy in identifying known ML models' architecture families under Ring 0 privileges and we demonstrated its effectiveness across different platforms. Moreover, our code is publicly available 1.
Najmeh Nazari, Chongzhou Fang, Hosein Mohammadi Makrani, Behnam Omidi, Mahdi Eslamimehr, Setareh Rafatirad, Avesta Sasan, Hossein Sayadi, Khaled N. Khasawneh, Houman Homayoun
DAC4
2024 SpecScope: Automating Discovery of Exploitable Spectre Gadgets on Black-Box Microarchitectures
abstract
Transient execution attacks pose information leakage risks in current systems. Disabling speculative execution, though mitigating the issue, results in significant performance loss. Accurate identification of vulnerable gadgets is essential for balancing security and performance. However, uncovering all covert channels is challenging due to complex microarchitectural analysis. This paper introduces SpecScope, a framework for automating the detection of Spectre gadgets in code using a black-box microarchitecture approach. SpecScope focuses on contention between transient and non-transient instructions to precisely identify and reduce false-positive Spectre gadgets, minimizing mitigation overhead. Tested on public libraries, SpecScope outperforms existing methods, reducing False-Positive rates by 8.9% and increasing True-Positive rates by 10.4%.
Najmeh Nazari, Behnam Omidi, Chongzhou Fang, Hosein Mohammadi Makrani, Setareh Rafatirad, Avesta Sasan, Houman Homayoun, Khaled N. Khasawneh
DATE2
2023 HeteroScore: Evaluating and Mitigating Cloud Security Threats Brought by Heterogeneity
Chongzhou Fang, Najmeh Nazari, Behnam Omidi, Han Wang 0020, Aditya Puri, Manish Arora, Setareh Rafatirad, Houman Homayoun, Khaled N. Khasawneh
NDSS3
2022 Repttack: Exploiting Cloud Schedulers to Guide Co-Location Attacks
Chongzhou Fang, Han Wang 0020, Najmeh Nazari, Behnam Omidi, Avesta Sasan, Khaled N. Khasawneh, Setareh Rafatirad, Houman Homayoun
NDSS4