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Lucas Ferreira Dos Santos Duarte

dblp:294/0623 · DBLP profile ↗
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2ranked-venue papers
0as first author
2since 2021 · last 2024
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Computer networks · 2 · 2 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Reconfigurable computing and FPGAs · 77% Hardware accelerators and domain-specific architectures · 23%
Computer networks
1 paper
Software-defined and programmable networks · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Software-defined and programmable networks
programmable data plane
0.812024
eBPFlow: A Hardware/Software Platform to Seamlessly Offload Network Functions Leveraging eBPF · IEEE/ACM Trans. Netw. 2024
Reconfigurable computing and FPGAs › FPGA-based network processing
FPGA-based network acceleration
0.812024
eBPFlow: A Hardware/Software Platform to Seamlessly Offload Network Functions Leveraging eBPF · IEEE/ACM Trans. Netw. 2024
Hardware accelerators and domain-specific architectures
network function acceleration
0.212024
eBPFlow: A Hardware/Software Platform to Seamlessly Offload Network Functions Leveraging eBPF · IEEE/ACM Trans. Netw. 2024

Methods — techniques the papers use, named apart from their topics

eBPF · 1.5FPGA implementation · 1.5
YearPublicationVenuePosition
2024 eBPFlow: A Hardware/Software Platform to Seamlessly Offload Network Functions Leveraging eBPF
abstract
NFV and SDN enable flexibility and programmability at the data plane. In addition, offloading packet processing to a hardware saves processing resources to compute other workloads. However, fulfilling requirements such as high throughput and low latency with a flexible and programmable data plane is challenging. This paper introduces eBPFlow, a platform for seamlessly accelerating network computation. It builds upon eBPF. eBPFlow combines flexibility and programmability in software with high performance using an FPGA. We implemented our system on the NetFPGA SUME, performing tests on a physical testbed. We built a range of NFs. Our results show that the eBPFlow supports offloading of NFs with throughput at the line rate, latency between$20~\mu \text{s}$and$40~\mu \text{s}$, communication with host, and consumption of 22 W. Moreover, eBPFlow processes 12.05 Mpps more than the kernel. eBPFlow has a throughput of 2.59 Gbps higher than the hXDP, a system similar to eBPFlow.
Racyus D. G. Pacífico, Lucas Ferreira Dos Santos Duarte, Luiz Filipe M. Vieira, Barath Raghavan, José A. M. Nacif, Marcos A. M. Vieira
IEEE/ACM Trans. Netw.2
2021 Application Layer Packet Classifier in Hardware
Racyus D. G. Pacífico, Matheus S. Castanho, Luiz Filipe M. Vieira, Marcos A. M. Vieira, Lucas Ferreira Dos Santos Duarte, José A. M. Nacif
IM5