Demo Data from SIGIR 2026 / reviewers in the wild / expert
Yom Nigam
dblp:297/4290
· DBLP profile ↗
2ranked-venue papers
0as first author
2since 2021 · last 2022
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 2 since 2021Software engineering, systems software and programming languages · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 75% Performance modeling and evaluation · 25% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Performance modeling and evaluation › simulation › architectural simulation
cycle-accurate simulation |
0.6 | 1 | 2022 | FastSim: A Fast Simulation Framework for High-Level Synthesis · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2022 |
Electronic design automation
hardware verification and test |
0.6 | 1 | 2022 | FastSim: A Fast Simulation Framework for High-Level Synthesis · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2022 |
Electronic design automation
high-level synthesis |
0.6 | 1 | 2022 | FastSim: A Fast Simulation Framework for High-Level Synthesis · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2022 |
Electronic design automation › hardware verification and test › hardware verification
high-level synthesis verification |
0.6 | 1 | 2022 | FastSim: A Fast Simulation Framework for High-Level Synthesis · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2022 |
Methods — techniques the papers use, named apart from their topics
cycle-accurate simulation · 0.6c simulation · 0.6RTL simulation · 0.6
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2022 | FastSim: A Fast Simulation Framework for High-Level SynthesisabstractHigh-level synthesis (HLS) is a well-established framework used to translate high-level algorithmic behaviors into hardware designs. Despite the enduring research efforts, a major prevailing bottleneck of HLS is the large gap between the design and verification processes. Presently, register transfer level (RTL) simulation is the primary platform used for HLS design verification. Although most of the state-of-the-art RTL simulators provide an abstracted user-friendly platform for verification, they are undesirably slow and sometimes incomprehensible to non-field-programmable gate array experts to debug. The alternative software simulators (C simulation) introduced by commercial HLS tools render faster simulation, but are not cycle accurate and are not capable to estimate design performance. In this article, we introduce an automatic cycle-accurate simulation tool, FastSim, that manipulates certain unique features of HLS design to extract a concise, well-indented, and debug-friendly C behavior from the synthesized RTL. Our simulation tool ensures RTL correctness, provides cycle accuracy, accurate performance estimation, and renders on an average around 300 times faster simulation compared to RTL simulators and comparable performance to that of software C simulators. Mohammed Abderehman, Jayprakash Patidar, Jay H. Oza, Yom Nigam, Abdul Khader Thalakkattu Moosa, Chandan Karfa |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 4 |
| 2021 | HOST: HLS Obfuscations against SMT ATtackabstractThe fab-less IC design industry is at risk of IC counterfeiting and Intellectual Property (IP) theft by untrusted third party foundries. Logic obfuscation thwarts IP theft by locking gate-level netlists using a locking key. The complexity of circuit designs and migration to high level synthesis (HLS) expands the scope of locking to a higher abstraction. Automated RTL locking during HLS integrates obfuscation into the backend HLS tool. This is tedious and requires access to the HLS tool source code. Furthermore, recent work proposed an SMT attack on HLS-based obfuscation. In this work, we propose sn RTL locking tool HOST, to thwart the SMT attack. The HOST approach is agnostic to the HLS tool. Results show that HOST obfuscations have low overhead and thwart SMT attacks. Chandan Karfa, Abdul Khader Thalakkattu Moosa, Yom Nigam, Ramanuj Chouksey, Ramesh Karri |
DATE | 3 |