Omnidirectional cameras have been used widely to better understand surrounding environments. They are often configured as stereo to estimate depth. However, due to the optics of the fish eye lens, conventional epipolar geometry is inapplicable directly to omnidirectional camera images. Intermediate formats of omnidirectional images, such as equirect-angular images, have been used. However, stereo matching performance on these image formats has been lower than the conventional stereo due to severe image distortion near pole regions. In this paper, to address the distortion problem of omnidirectional images, we devise a novel subdivision scheme of a spherical geodesic grid. This enables more isotropic patch sampling of spherical image information in the omnidirectional camera space. By extending the existing equalarc scheme, our spherical geodesic grid is tessellated with an equalepiline subdivision scheme, making the cell sizes and in-between distances as uniform as possible, i.e., the arc length of the spherical grid cell's edges is well regularized. Also, our uniformly tessellated coordinates in a 2D image can be transformed into spherical coordinates via one-to-one mapping, allowing for analytical forward/backward transformation. Our uniform tessellation scheme achieves a higher accuracy of stereo matching than the traditional cylindrical and cubemap-based approaches, reducing the memory footage required for stereo matching by 20%.

Accurate stereo matching requires a large amount of memory at a high bandwidth, which restricts its use in resource-limited systems such as mobile devices. This problem is compounded by the recent trend of applications requiring significantly high pixel resolution and disparity levels. To alleviate this, we present a memory-efficient and robust stereo matching algorithm. For cost aggregation, we employ the semiglobal parametric approach, which significantly reduces the memory bandwidth by representing the costs of all disparities as a Gaussian mixture model. All costs on multiple paths in an image are aggregated by updating the Gaussian parameters. The aggregation is performed during the scanning in the forward and backward directions. To reduce the amount of memory for the intermediate results during the forward scan, we suggest to store only the Gaussian parameters which contribute significantly to the final disparity selection. We also propose a method to enhance the overall procedure through a learning-based confidence measure. The random forest framework is used to train various features which are extracted from the cost and intensity profile. The experimental results on KITTI dataset show that the proposed method reduces the memory requirement to less than 3 percent of that of semiglobal matching (SGM) while providing a robust depth map compared to those of state-of-the-art SGM-based algorithms.

Anticipation of accidents ahead of time in autonomous and non -autonomous vehicles aids in accident avoidance. In order to recognize abnormal events such as traffic accidents in a video sequence, it is important that the network takes into account interactions of objects in a given frame. We propose a novel Feature Aggregation (FA) block that refines each object's features by computing a weighted sum of the features of all objects in a frame. We use FA block along with Long Short Term Memory (LSTM) network to anticipate accidents in the video sequences. We report mean Average Precision (mAP) and Average Time-to-Accident (ATTA) on Street Accident (SA) dataset. Our proposed method achieves the highest score for risk anticipation by predicting accidents 0.32 sec and 0.75 sec earlier compared to the best results with Adaptive Loss and dynamic parameter prediction based methods respectively.

Neural Architecture Search (NAS) has gained attraction due to superior classification performance. Differential Architecture Search (DARTS) is a computationally light method. To limit computational resources DARTS makes numerous approximations. These approximations result in inferior performance. We propose to fine-tune DARTS using fixed operations as they are independent of these approximations. Our method offers a good trade-off between the number of parameters and classification accuracy. Our approach improves the top-1 accuracy on Fashion-MNIST, CompCars, and MIO-TCD datasets by 0.56%, 0.50%, and 0.39%, respectively compared to the state-of-the-art approaches. Our approach performs better than DARTS, improving the accuracy by 0.28%, 1.64%, 0.34%, 4.5%, and 3.27% compared to DARTS, on CIFAR-10, CIFAR-100, Fashion-MNIST, CompCars, and MIO-TCD datasets, respectively.

Most very-large-scale integration (VLSI) designs of the global optical flow method focus on reducing external memory accesses due to global and iterative processes for low-power operation in mobile systems. However, to achieve this goal, considerable amounts of resources are used and the throughput is decreased. To address these issues, we propose a multirow-based propagation approach and an efficient VLSI architecture. This approach divides an image into multiple small subimages. The flow of each subimage is then estimated sequentially using a small amount of internal memory without accessing any external memory. To avoid discontinuity artifacts stemming from the boundaries of the subimages, boundary conditions are imposed based on the smoothness of the optical flow. In addition, the main equations of the global optical flow method are simplified to boost the processing speed. The experimental results demonstrate that the external memory bandwidth is reduced by 96.7% with negligible accuracy degradation. Furthermore, the proposed design uses 63.4%-98% less internal memory and achieves $1.9\times $ -$18.8\times $ higher throughput-per-watt compared to state-of-the-art designs of the global optical flow method.

Network compression reduces the computational complexity and memory consumption of deep neural networks by reducing the number of parameters. In SVD-based network compression the right rank needs to be decided for every layer of the network. In this paper we propose an efficient method for obtaining the rank configuration of the whole network. Unlike previous methods which consider each layer separately, our method considers the whole network to choose the right rank configuration. We propose novel accuracy metrics to represent the accuracy and complexity relationship for a given neural network. We use these metrics in a non-iterative fashion to obtain the right rank configuration which satisfies the constraints on FLOPs and memory while maintaining sufficient accuracy. Experiments show that our method provides better compromise between accuracy and computational complexity/memory consumption while performing compression at much higher speed. For VGG-16 our network can reduce the FLOPs by 25% and improve accuracy by 0.7% compared to the baseline, while requiring only 3 minutes on a CPU to search for the right rank configuration. Previously, similar results were achieved in 4 hours with 8 GPUs. The proposed method can be used for lossless compression of a neural network as well. The better accuracy and complexity compromise, as well as the extremely fast speed of our method make it suitable for neural network compression.

Numerous camera sensors have been recently proposed to estimate the depth of objects in the scene. However, many of these sensors either require multiple imaging elements or an active illuminant. In this paper, we propose a new depth camera, termed offset aperture (OA) camera, which provides depth of the scene with a single shot without an active illuminant. The camera is based on a 4-color sensor that senses the infrared (IR) signal along with the visible RGB signals. Separate OAs are used for IR and RGB images. A depth-dependent disparity is generated between the IR and RGB images. There is no disparity across the R, G, and B channel images, which allows the RGB image to be well-aligned. Numerous techniques are used in this work to observe good-quality depth maps and images. Leakage compensation has been proposed to remove crosstalk between the IR and RGB images. A comparison with another 4-color sensor called Dual Aperture camera shows that OA camera provides 88% improvement in depth sensitivity and 45% improvement in color quality, on average. The proposed OA camera can be used for numerous applications including occlusion handling in stereo, selective focus, and night vision. The advantages of the proposed OA camera include competitive image quality, capability of depth extraction, well-aligned RGB images, and small footprint of the camera, which make OA camera a suitable candidate for mobile applications.

Crowd anomaly detection is a key research area in vision-based surveillance. Most of the crowd anomaly detection algorithms are either too slow, bulky, or power-hungry to be applicable for battery-powered surveillance cameras. In this paper, we present a new crowd anomaly detection algorithm. The proposed algorithm creates a feature for every superpixel that includes the contribution from the neighboring superpixels only if their direction of motion conforms with the dominant direction of motion in the region. We also propose using univariate Gaussian discriminant analysis with the K-means algorithm for classification. Our method provides superior accuracy over numerous deep learning-based and handcrafted feature-based approaches. We also present a low-power FPGA implementation of the proposed method. The algorithm is developed such that features are extracted over non-overlapping pixels. This allows gating inputs to numerous modules resulting in higher power efficiency. The maximum energy required per pixel is 2.43 nJ in our implementation. 126.65 Mpixels can be processed per second by the proposed implementation. The speed, power, and accuracy performance of our method make it competitive for surveillance applications, especially battery-powered surveillance cameras.

This paper presents a Offset Aperture (OA) based single camera system and proposes a optimized vision processor, a new hardware architecture for fast, low-energy, and low-complexity depth extraction. The proposed design was fabricated in 110nm CMOS image sensor technology and supports 32-level depth resolution on 1920×1080 full HD image with 30fps, consuming 280.53mW from 1.5V supply and a mere 2.8% of bad classification. The low-complexity algorithms are employed to eliminate the DRAM access, thereby the proposed OA architecture can be directly embedded with the CMOS image sensor and commercial image processing chip.

Accurate stereo matching for depth extraction requires a large memory space, which restricts its use in resource-limited systems. The problem is aggravated by the recent trend of applications requiring significantly high pixel resolution and disparity levels. To alleviate the high memory requirement, we propose to represent the aggregation costs as a Gaussian mixture model (GMM) function. Only a set of GMM parameters is stored and used instead of all the costs for each pixel. We also propose GMM parameter update-based aggregation along multiple paths. To preserve the accuracy of the disparity map, we employ a depth confidence measure and propose an update rule for the slanted surface of an object. Experimental results over the KITTI dataset show that the proposed method reduces the memory requirement to less than 5% of that of semiglobal matching, while the accuracy is maintained at the level of state-of-the-art semiglobal and local methods.

Due to the increasing demand for 3D applications, development of novel depth-sensing cameras is being actively pursued. However, most of these cameras still face the challenge of high energy consumption and slow speed in the depth extraction process. This becomes a serious bottleneck in embedded implementations where real-time performance is required, constrained by power and area. This work proposes Offset Aperture (OA) camera, a new hardware architecture for fast, low-energy, and low-complexity depth extraction. Optimal implementations of pre-processing, cost-volume generation and cost-aggregation are presented. The whole depth-extraction pipeline has been implemented on a Field Programmable Gate Array (FPGA). Overall, a mere 2.8% of bad classification was achieved with the proposed system. Also, the proposed system can process 37 VGA frames per second while consuming 0.224 μJ/pixel. High accuracy, speed and low energy consumption of the proposed OA architecture make it suitable for embedded applications.

Pedestrian detection is a key problem in computer vision and is currently addressed with increasingly complex solutions involving compute-intensive features and classification schemes. In this scope, histogram of oriented gradients (HOG) in conjunction with linear support vector machine (SVM) classifier is considered to be the single most discriminative feature that has been adopted as a stand-alone detector as well as a key instrument in advance systems involving hybrid features and cascaded detectors. In this paper, we propose a pedestrian detection framework that is computationally less expensive as well as more accurate than HOG-linear SVM. The proposed scheme exploits the discriminating power of the locally significant gradients in building orientation histograms without involving complex floating point operations while computing the feature. The integer-only feature allows the use of powerful histogram inter-section kernel SVM classifier in a fast lookup-table-based implementation. Resultantly, the proposed framework achieves at least 3% more accurate detection results than HOG on standard data sets while being 1.8 and 2.6 times faster on conventional desktop PC and embedded ARM platforms, respectively, for a single scale pedestrian detection on VGA resolution video. In addition, hardware implementation on Altera Cyclone IV field-programmable gate array results in more than 40% savings in logic resources compared with its HOG-linear SVM competitor. Hence, the proposed feature and classification setup is shown to be a better candidate as the single most discriminative pedestrian detector than the currently accepted HOG-linear SVM.

Background subtraction (BS) is a crucial machine vision scheme for detecting moving objects in a scene. With the advent of smart cameras, the embedded implementation of BS finds ever-increasing applications. This paper presents a new BS scheme called efficient BS for smart cameras (EBSCam). EBSCam thresholds the change in the estimated background model, which suppresses variance of the estimates, resulting in competitive performance compared with standard BS schemes. The percentage of wrong classification of EBSCam is lower than those of the Gaussian mixture model (GMM) (10.97%) and the pixel-based adaptive segmenter (PBAS) (4.66%) algorithms in FPGA implementations. Moreover, the memory bandwidth requirement of EBSCam is 6.66%, 41.36%, and 90.48% lower than the state-of-the-art FPGA implementation of GMM, ViBe, and PBAS algorithms, respectively. EBSCam achieves a significant speed up compared with the FPGA implementations of GMM (by 43.3%), ViBe (by 118.6%), and PBAS (by 144.8%) schemes. Similarly, the energy consumption of EBSCam is 80.56% and 99.9% less compared with GMM and PBAS, respectively. In summary, the advantages of EBSCam in accuracy, speed, and energy consumption combined together make it especially suitable for embedded applications.

Nonvolatile magnetic RAM (MRAM) offers high cell density and low leakage power. This paper reports on using a 3-D integration technology based on through-silicon vias, to stack disparate memory technologies (e.g., SRAM and MRAM) together onto chip multiprocessors. In this paper, we explore the design of a 3-D stacked nonuniform hybrid SRAM/MRAM L2 cache architecture (NUCA) using the on-chip network to mitigate the interconnection problem. In addition, this paper investigates the problem of partitioning shared SRAM/MRAM hybrid L2 cache and placing cache data into the partitioned 3-D stacked hybrid NUCA for concurrently executing multiple applications in order to improve the system performance in terms of instructions per second while considering the heterogeneous characteristics in interconnection wire delay, memory cell density, memory access latency, and memory power consumption in a 3-D stacked hybrid SRAM/MRAM L2 cache. Experimental results show that the proposed runtime method with a 3-D stacked hybrid L2 cache improves performance by 61%, energy efficiency, i.e., energy-delay product by 53%, and storage lifetime by 15.6 times on average compared with the conventional SRAM-only L2 cache or MRAM-only L2 cache with the similar area.

This paper presents a solar energy harvesting (EH) system to power a portable compact LED lamp, which can be charged during daytime and used to light during night time. The solar lamp consists of three PV panels, an EH and power management circuit, three NiMH rechargeable batteries, and an LED. A commercial off-the-shelf chip TI BQ25504 is used to prototype the EH and power management circuit for the proposed system. Experimental results show that the proposed PV system can harvest solar energy both in indoor and outdoor environments. The peak net power harvested by the proposed system is about 380 mW on a sunny day, 250 mW on a partly cloudy day, and 30 mW on a cloudy day.

Pedestrian detection has lately attracted considerable interest from researchers due to many practical applications. However, the low accuracy and high complexity of pedestrian detection has still not enabled its use in successful commercial applications. In this paper, we present insights into the complexity-accuracy relationship of pedestrian detection. We consider the Histogram of Oriented Gradients (HOG) scheme with linear Support Vector Machine (LinSVM) as a benchmark. We describe parallel implementations of various blocks of the pedestrian detection system which are designed for full-HD (1920×1080) resolution. Features are improved by optimal selection of cell size and histogram bins which have been shown to significantly affect the accuracy and complexity of pedestrian detection. It is seen that with a careful choice of these parameters a frame rate of 39.2 fps is achieved with a negligible loss in accuracy which is 16.3x and 3.8x higher than state of the art GPU and FPGA implementations respectively. Moreover 97.14% and 10.2% reduction in energy consumption is observed to process one frame. Finally, features are further enhanced by removing petty gradients in histograms which result in loss of accuracy. This increases the frame rate to 42.7 fps (18x and 4.1x higher) and lowers the energy consumption by 97.34% and 16.4% while improving the accuracy by 2% as compared to state of the art GPU and FPGA implementations respectively.

Nonvolatile memory such as magnetic RAM (MRAM) offers high cell density and low leakage power while suffering from long write latency and high write energy, compared with SRAM. 3-D integration technology using through-silicon vias enables stacking disparate memory technologies (e.g., SRAM and MRAM) together onto chip-multiprocessors (CMPs). The use of hybrid memories as an on-chip cache can take advantage of the best characteristics that each technology offers. However, the inherent high power density and heat removal limitation in 3-D integrated circuits may incur temperature-related problems. In this paper, we propose a runtime thermal management method for CMPs with the 3-D stacked hybrid SRAM/MRAM L2 cache. The proposed method combines dynamic cache management such as resource allocation, way-based power gating, and data migration with dynamic voltage and frequency scaling of processing cores in a temperature- and energy-aware manner. Experimental results show that the proposed runtime method with the 3-D stacked hybrid L2 cache offers up to 107.37% (55.28% on average) performance improvement and 88.47% (47.65% on average) energy efficiency improvement compared with existing thermal management methods with 3-D stacked SRAM-based L2 cache.

Energy consumption is a crucial issue of mobile surveillance cameras owing to limited battery capacity. The lifetime of the system is significantly extended by the event-driven operation; the system mostly stays in sleep mode and wakes up only when an event is detected. In this paper, we propose a design of a low-energy surveillance camera that records events such as the abnormal movement of objects, or physical damage to the camera itself. Unlike conventional event-driven approaches, the proposed system records video from 10 seconds before the event detection because the most critical information is often before or at the moment of event detection, not after the detection. Two different encoders, a low-power encoder and a high-compression encoder, are employed together to implement the low-energy surveillance camera. Experimental results show that the energy consumption of the whole system is reduced by up to 74.9% (by 66.8% on average) compared with conventional always-on system.

CCTV-based surveillance systems gaining widespread popularity still waste computational power, transmission bandwidth and storage space. This paper tries to respond to this necessity by proposing a motion-based video recording scheme with dual frame rate motion detection. Statistical models for memory and energy consumption of the overall system are described. Root-mean-square error of the models for memory consumption is 0.54 and 0.78 for systems with single frame rate and dual frame rate motion detection, respectively. For a typical surveillance video, the proposed dual frame rate system stores 1.22, 4.94, 7.81 less frames per second on at 10fps, 1fps, 0.5fps respectively, compared to the single frame rate motion detection system. We have suggested a criterion for using dual frame rate motion detection in surveillance based on a mathematical model.

This paper proposes a method to prolong the lifetime of event-driven wireless video sensor networks. The proposed method provides the operating point of each node by firstly selecting the route to the sink node in an energy-aware fashion. Then it finds the lifetime-maximal encoding bit-rate utilizing the event statistics and the analytic power consumption models of major functional blocks in the target video sensor node, i.e., video encoder and wireless transceiver. Furthermore, it additionally controls the encoding frame-rate to balance the lifetime of each node within the selected route when the distribution of event occurrence rate is significantly unbalanced. Experimental results show that the proposed algorithm extends the lifetime of the network by 183.53% on average compared with a conventional bit-rate allocation method.

Ultra-low voltage VLSI designs are gaining widespread attention due to the requirements of minimum energy consuming motes. Leakage energy is a considerable part of the overall energy consumed in the ultra-low voltage domain. This paper deals with the overall energy reduction in ultra-low power systems by the use of digit-serial implementations. Leakage energy is reduced by the reduction of hardware in digit-serial implementations. However, overhead circuitry adds to the energy budget. It has been shown in this paper that digit-serial implementations do reduce the overall energy consumption in the ultra-low power VLSI circuits compared to bit-serial and wordparallel implementations. 73% and 92% reduction in energy per clock cycle was obtained with an 8-bit adder at a source voltage of 0.7V compared to the bit-serial and word-parallel implementations respectively.

In this paper surveillance system employing background subtraction scheme is discussed. The aim of the work is to minimize the waste energy of the overall system due to false positives. Pixels in the foreground of a motion detection system remain non-zero even if a moving object has stopped due to the settling time associated with an adaptive background subtraction scheme as Mixture of Gaussians. Temporal variance in a visually static pixel region also triggers false positives. Optimal learning rate for different parameters as threshold values, ROI size and total number of frames in the scene has been derived in this paper.

Three-dimentional (3D) integration is one of the most promising approaches to increase cache bandwidth and to reduce the wire length and thereby, the delay and transmission power consumption. However, high power density in 3D IC due to dense integration incurs significant leakage current increment which leads to high static energy consumption. The leakage energy consumption of 3D-stacked cache memory is more serious than that of conventional cache memory in 2D ICs. In this paper, we propose a selective cache compression technique coupled with power gating to reduce the static energy consumption of 3D-stacked SRAM cache. Cache blocks are selected to be compressed in runtime according to the cache access pattern, so that the decompression overhead is reduced. The experimental results show that our method reduces energy consumption by up to 40% (22% on average) with negligible performance overhead compared with the conventional cache management policy.

In this paper, we propose an event-driven black box surveillance camera which reduces energy consumption by waking up the system only when an event is detected and dynamically adjusting the video encoding and the resultant image distortion according to the criticality of captured frames called significance level. To achieve this goal, we find an encoding bitrate minimizing the energy consumption of the camera while satisfying the limited memory space constraint and distortion requirement at each significance level by judiciously allocating bit-rate to each significance level. To do that, we considered the trade-off relations between the total energy consumption vs. encoding bit-rate according to the significance level. For further energy savings, we also proposed a low complexity solution which adjusts the energy-minimal encoding bit-rate based on the dynamically changing event behavior, i.e., timing and duration of events. Experimental results show that the proposed method yields up to 67.49% (49.19% on average) energy savings compared to the conventional bitrate allocation methods.

Recently, hybrid cache architecture has become illuminated. As heterogeneous memory dies are stacked, it improves the performance of microprocessor enhanced in terms of power consumption and processing speed. This paper analyzed the hybrid cache architecture using different programs and memory types. SRAM is fixed for L1 cache memory, whereas DRAM, MRAM, and PRAM are the candidates for L2 cache memory. Each memory structure has the area satisfying the least Average Memory Access Time (AMAT) under a given area condition. Architecture composed of SRAM and MRAM shows 16.9% reduction in average memory access time and 15.2% of power reduction compared with that composed of homogeneous SRAM. Structure of SRAM and DRAM represents 33.0% reduction in power consumption, and that of SRAM and PRAM shows a potential to reduce area and power consumption due to their high density.

Growing needs for surveillance in locations without power lines necessitates the development of a surveillance camera with extremely low-power consumption and an assured stable operation until the time of expected run-out of available energy. This paper proposes an algorithm for scheduling of video encoding configurations in a battery-operated surveillance system to reduce the image distortion while assuring the sustained operation until the battery recharge/exchange. The optimal video encoding configuration is determined based on the amount of estimated remaining event duration (considering the uncertainty of events) and remaining battery charge (considering the rate-capacity and recovery effect). The proposed algorithm consists of two steps: design-time step and run-time step. In the design-time step, prediction of remaining event duration, called duration prediction, is performed considering the uncertainty of events and tradeoff between encoding power and image quality. During run-time, video encoding configuration is switched between intra-frame encoding and inter-frame encoding based on the duration prediction obtained in design-time step and the remaining battery charge measured in run-time step. Compared to the conventional method based on the most conservative duration prediction , experimental results show that the proposed method provides 2.24~3.78 dB improvement in the image quality (in terms of peak signal-to-noise ratio in the H.264 encoding of four video sequences while satisfying the battery constraint.

Power and delay induced from long on-chip interconnections are becoming major issues of chip multiprocessor design. Both network-on-chip (NoC) and three-dimensional integration are promising ways to mitigate the interconnection problem. In this paper, we explore the design of 3Dstacked non-uniform cache architecture (NUCA) with onchip network. In addition, this paper investigates the problem of partitioning shared L2 cache for concurrently executing multiple applications in order to improve the system performance in terms of instructions per cycle. The proposed design is evaluated in an integrated power, performance, and temperature simulator. Experimental results show that the proposed method enhances system performance by 23.3% and reduces energy consumption by 17.9% for 16-core processor system compared to conventional design.

In battery-operated wireless video surveillance systems (WVSS), it is mostly required to detect events in an energy-efficient manner due to limited available energy and a huge amount of data to be processed. Therefore, one of the main challenges in the battery-constrained systems is to minimize the energy consumption of the whole system. In this paper, we present an energy-aware event detector which has a hierarchical decision architecture to maximize the system lifetime while achieving the required detection accuracy. An analytical model for the relationship between the complexity of the event detector and system performance is derived based on the given event characteristics. Finally, we suggest a heuristic search algorithm to significantly reduce the heavy computational complexity. Experimental results have shown that the proposed heuristic search algorithm provides 98.17% complexity reduction on average with a negligible deterioration of the system lifetime.

In this paper, we propose a lifetime maximization method for battery- and flash-constrained blackbox surveillance node (BSN) consisting of image sensor, event detector, video encoder, flash memory and battery. Because it is not economically feasible to transfer all the recorded images to the base station due to the limited energy in BSN, the recorded images are stored in flash memory for offline event recognition. In BSN, balancing the usage of battery and flash memory is critical to prolong the lifetime, because the shortage of either battery charge or flash capacity could lead to a complete loss of events, or a significant loss of quality in the recorded image of events. The lifetime of BSN is determined by the remaining battery charge and flash memory space. In this work, we assume that the resources of BSN, i.e., battery and flash memory are refreshed every system maintenance period (SMP). The proposed method controls the bit-rate of encoded videos and sampling rate, i.e., resolution and frame rate, to prolong the BSN lifetime till the SMP. Experimental results show that the proposed method prolongs the BSN lifetime by up to 136.36% compared with an existing bit-rate allocation method which does not consider the resource usage balancing.

We proposed a scheme to improve the lifetime of multi-camera system and the quality of its captured image by appropriate sharing of such resources among camera nodes as battery and memory based on low-power wireless communication links among camera nodes. The proposed scheme determines which camera node captures the event and which camera node stores the captured event by jointly considering residual battery charge, remaining memory space, wireless communication overhead, and the image quality captured by each camera node. Experimental result has shown that the proposed scheme achieves up to 4x lifetime extension as well as 43.19% improvement of the image quality (as measured by the face detection rate) compared to a conventional method [12].

Three-dimensional (3D) memory stacking, which enables stacking memory on top of a microprocessor or chip-multiprocessor (CMP), is one of the most promising applications of 3D integration technology to meet memory bandwidth challenges. However, the high power density, i.e., power dissipation per unit volume due to the high integration incurs temperature-related problems such as reliability of 3D-stacked memory. Error correcting codes (ECCs) are commonly used to deal with soft errors and thereby enhance system reliability. In this paper, we present the effects of temperature, refresh period, and ECC policy on the reliability and power consumption of 3D-stacked embedded DRAM (eDRAM). To minimize the energy consumption of the 3D-stacked eDRAM without violating error rate limitation, refresh period and ECC policy must be controlled in a temperature-aware manner. Experimental results show that the proposed adaptive ECC policy with varying temperature achieves a reduction of energy consumption by up to 26% compared with fixed ECC policy under a given error rate constraints.

Demands for high performance are growing rapidly and multiple processor cores and huge caches are required to meet these requirements. 3D integration provides us a very bright option to encounter this by integrating numerous cores and cache layers in a single chip. Temperature however becomes a problem in 3D integration due to increased power density. A methodology to exploit maximum performance while keeping the temperature under a given limit has been proposed in this paper. We have solved for the optimum clock frequencies, cache capacity and the placement of cache banks for each core to get the maximum throughput. Experiments are done on multiple benchmark programs and a peak 53% and an average 49% improvement in performance as compared to the base case which assigns same frequency and number of banks to each core is found.

3-D integration is a new technology that overcomes the limitations of 2-D integrated circuits, e.g., power and delay induced from long interconnect wires, by stacking multiple dies to increase logic integration density. However, chip-level power and peak temperature are the major performance limiters in 3-D multi-core architectures. In this paper, we propose a runtime power management method for both peak power and temperature-constrained 3-D multi-core systems in order to maximize the instruction throughput. The proposed method exploits dynamic temperature slack (defined as peak temperature constraint minus current temperature) and workload characteristics (e.g., instructions per cycle and memory-boundness) as well as thermal characteristics of 3-D stacking architectures. Compared with existing thermal-aware power management solutions for 3-D multi-core systems, our method yields up to 34.2% (average 18.5%) performance improvement in terms of instructions per second without significant additional energy consumption.

Most complex software programs are characterized by program phase behavior and runtime distribution. Dynamism of the two characteristics often makes the design-time workload prediction difficult and inefficient. Especially, memory stall time whose variation is significant in memory-bound applications has been mostly neglected or handled in a too simplistic manner in previous works. In this paper, we present a novel online dynamic voltage and frequency scaling (DVFS) method which takes into account both program phase behavior and runtime distribution of memory stall time, as well as computational workload. The online DVFS problem is addressed in two ways: intraphase workload prediction and program phase detection. The intraphase workload prediction is to predict the workload based on the runtime distribution of computational workload and memory stall time in the current program phase. The program phase detection is to identify to which program phase the current instant belongs and then to obtain the predicted workload corresponding to the detected program phase, which is used to set voltage and frequency during the program phase. The proposed method considers leakage power consumption as well as dynamic power consumption by a temperature-aware combined Vdd/Vbbscaling. Compared to a conventional method, experimental results show that the proposed method provides up to 34.6% and 17.3% energy reduction for two multimedia applications, MPEG4 and H.264 decoder, respectively.

Success of workload prediction, which is critical in achieving low energy consumption via dynamic voltage and frequency scaling (DVFS), depends on the accuracy of modeling the major sources of workload variation. Among them, memory stall time, whose variation is significant especially in case of memory-bound applications, has been mostly neglected or handled in too simplistic assumptions in previous works. In this paper, we present an analytical DVFS method which takes into account variations in both computation and memory stall cycles. The proposed method reduces leakage power consumption as well as switching power consumption through combined Vdd/Vbbscaling. Experimental results on MPEG4 and H.264 decoder have shown that, compared to previous methods and, our method achieves up to additional 30.0% and 15.8% energy reductions, respectively.

As the video resolution increases, high computational complexity of the fractional motion estimation (FME) introduces difficulty to meet real-time constraints in a video coding. In this paper, we proposed a single-pass FME algorithm and its architecture with low hardware cost and negligible loss of the image quality. The proposed algorithm directly searches only surroundings of both the predicted fractional motion vector and the search center. To reduce the hardware cost of processing units in the proposed FME architecture, bit clipping scheme is applied to processing units reducing the hardware cost by 25%. Experimental results show that the proposed algorithm provides almost the same rate-distortion performance as the full-search algorithm. The result of hardware implementation shows that a quad full high definition video (4096×2160) can be processed in real time (24 frame/sec) using 134k gates when the operating frequency is 250MHz. Compared with the recent work supporting quad full high definition video, the proposed FME architecture has shown 70% reduction of the hardware cost.

An event criticality-aware wireless surveillance system tries to minimize the energy consumption by adjusting the image distortion (or quality) requirement according to event criticality. In this paper, we present a novel video encoding method which scales bitrate so as to minimize the energy consumption of the wireless surveillance system while satisfying the given memory constraint. Given event statistics, memory size, and distortion requirement, the presented method gives an energy-optimal bitrate based on an analytic formulation of energy-rate-distortion (E-R-D) relationship for the target system consisting of H.264 video encoder, event detector, transceiver and memory. Experimental results show that the proposed method offers up to 59.6% (29.1% on average) energy savings compared to an existing bitrate allocation method which does not consider event statistics.

In frame memory recompression, decompression latency consists of two components, i.e., memory access cycles for compressed data fetch, and decompression time. Compared to most earlier works which mainly focused on the compression ratio and, therefore, only reducing memory access cycles, this paper proposes a low-latency variable-length coding method called non-zero bit selection scheme (NBS). The proposed NBS enables highly parallel decompression achieving a three-cycle decompression for an 8×8 block, compared to previous methods requiring as many as twelve clock cycles for the case of exponential Golomb code. It is notable that the proposed NBS scheme has achieved this without deterioration of the compression ratio. Experimental result on a number of full HD videos shows that the compression ratio of the proposed method is at least not worse than that obtained with the exponential Golomb code on the average, while reducing the decompression time to 25% compared to the exponential Golomb code.

Increasing number of processor cores on a chip is a driving force to move to three-dimensional integration. On the other hand, as the number of processor cores increases, non-uniform cache architecture (NUCA) receives growing attention. Reducing effective memory access time, including cache hit time and miss penalty, is crucial in such multi-processor systems. In this paper, we propose a Latency-aware Utility-based Cache Partitioning (LUCP) method which reduces memory access time in a 3D-stacked NUCA. To reduce the memory access time, the proposed method partitions shared NUCA cache for each processor core according to latency variation (depending on the physical distance from processor core to cache bank) and cache access characteristic of application programs. Experimental results show that the proposed method reduces memory access time by up to 32.6% with an average of 14.9% compared to conventional method.

As technology scales, increasing capacity of cache memory leads to increase in leakage power dissipation, especially in three-dimensional (3D) IC with high thermal density. In this paper, we explore how cache data can be mapped on a multi-processor architecture in 3D IC to minimize energy consumption with considering temperature distribution and bus traffic congestion. Simulation results based on ILP (Integer Linear Programming) formulation show that the proposed cache data mapping approach achieves up to 30.7% energy reduction compared to the case of considering temperature distribution only.

Crossbar switch network has an increasing impact on such critical measures as throughput, latency, area, and power consumption of complex system-on-chip as technology scales to deep submicrometer. With high clock frequency crossbar switch network design, global wire delay and pipeline registers inserted for throughput are important because they affect area, frequency, and power consumption of the chip. The traffic congestion is also a very important factor because it leads to the lowering of throughput of the crossbar switch network. In this paper, we present a topology synthesis method for the low-power cascaded crossbar switch network satisfying the given bandwidth, latency, frequency, and area constraints. Unlike previous papers, our paper considers wire delay, traffic congestion, and pipeline register insertion at the same time. Experimental results show that the topologies optimized for power consumption for a given clock frequency consume less power than existing methods by up to 38.04%.

At high-operating temperature, chip cooling is crucial due to the exponential temperature dependence of leakage current. However, traditional cooling methods, e.g., power/clock gating applied when a temperature threshold is reached, often cause excessive performance degradation. In this paper, we propose a method for delivering lower energy consumption by integrating the cooling and running in a temperature-aware manner without incurring performance penalty. In order to further reduce the energy consumption, we exploited the runtime distribution of each sub-segment of a task called “bin” in an analytical manner such that time budget for cooling in each bin is allocated in proportion to the probability of the occurrence of the bin. We apply the proposed method to two realistic software programs, H.264 decoder and ray tracing and a benchmark program, equake. The experimental results show that the proposed method yields additional 19.4%-27.2% reduction in energy consumption compared with existing methods.

In H.264/AVC coders, the optimal mode decision for each coding unit is achieved based on a calculation of the rate-distortion (R-D) cost for each candidate mode. In this letter, we propose a context-adaptive binary arithmetic coding (CABAC)-based rate estimation scheme that reduces the computational complexity of the R-D cost function evaluation. The complex and time-consuming calculation of the arithmetic coding is replaced by a table lookup based on the proposed CABAC rate model for fast rate estimation. The context modeling part of CABAC is also simplified to accelerate the rate estimation process. The experimental results show that the proposed estimator follows the actual rate with the coefficient of determination$R^2 = 0.9997$. The proposed estimator yields about a 30% reduction in the computational complexity of the R-D optimized mode decision, thereby accelerating the entire encoder by about 17% to 25% with almost no degradation in the R-D performance.

Embedded compression is commonly employed in a video codec to reduce the data traffic to/from off-chip frame memory. We proposed a method for maintaining the memory bandwidth requirement at a significantly reduced level through dynamic search range adjustment for the motion estimation based on the observed relationship between the compression ratio and the motion vector. This, together with the so-called “center moving” to adjust the newly incoming macroblocks, helped significantly lower the requirement of the memory bandwidth without a fluctuation. Experimental results have shown that the memory bandwidth requirement can be finally stabilized to 20% of that of the full search. The image quality degradation was merely 0.02 dB.

Increasing the image size of a video sequence aggravates the memory bandwidth problem of a video coding system. Despite many embedded compression (EC) algorithms proposed to overcome this problem, no lossless EC algorithm able to handle high-definition (HD) size video sequences has been proposed thus far. In this paper, a lossless EC algorithm for HD video sequences and related hardware architecture is proposed. The proposed algorithm consists of two steps. The first is a hierarchical prediction method based on pixel averaging and copying. The second step involves significant bit truncation (SBT) which encodes prediction errors in a group with the same number of bits so that the multiple prediction errors are decoded in a clock cycle. The theoretical lower bound of the compression ratio of the SBT coding was also derived. Experimental results have shown a 60% reduction of memory bandwidth on average. Hardware implementation results have shown that a throughput of 14.2 pixels/cycle can be achieved with 36 K gates, which is sufficient to handle HD-size video sequences in real time.

This paper proposes a motion estimation scheme to reduce the computational complexity of multilayer motion estimation for scalable video coding. Based on the result of the motion estimation of the lower resolution layer referred to as base layer, we developed a new approach for exploring the search range of the enhancement layer with high coding efficiency. This approach is based on the activity defined as the absolute difference between the motion vector predictor and the final motion vector. Based on the correlation of the activities between neighboring layers, an inter-layer activity model was developed using a curve-fitted linear equation to exploit the activity in the base layer for deciding the search center and the search range of the enhancement layer. Each activity pair in the neighboring layers is used to associate the relevant macroblock to one of two groups; boundary region and interior region. The base-layer motion vector predictor is basically selected over all the activity regions; for each activity region, the proposed motion estimation algorithm decides whether to include the median motion vector predictor or not. Minimal sufficient search range is also decided from the inter-layer activity prediction factor that is adjusted to the given sequence. The proposed scheme reduced the execution time of motion estimation by 99.26% at the cost of 1.56% bit-rate increase and 0.048 dB peak signal-to-noise ratio (PSNR) decrease on average compared with the conventional full-search algorithm. The fast full-search block matching algorithm can also be incorporated to obtain the extra CPU time reduction in the motion estimation process. By adopting the fast full-search block matching algorithm (FFSBMA) in JSVM reference software, the CPU time was reduced by up to 91.84% and the memory bandwidth was reduced by 90% at the sacrifice of 1.27% bit-rate increase and 0.041 dB PSNR decrease on average compared with the FFSBMA only.

This paper presents a high-throughput, cost-effective implementation of six different integer transforms in the H.264/AVC high-profile coders, i.e., 4$\times$4 forward, 4$\times$4 inverse, forward Hadamard, inverse Hadamard, 8$\times$8 forward, and 8$\times$8 inverse transform, all integrated as a shared hardware. The 4$\times$4 transform matrices are regularized by using permutation, partitioned into 2$\times$2 blocks, and factored for maximal hardware sharing. By using two types of 4$\times$4 transform matrices included in an 8$\times$8 transform matrix, two different 8$\times$8 transforms are both described as three steps and unified with minor modification. To improve throughput of the transform, two independent 4$\times$4 transform blocks within the 8$\times$8 transform block operate in parallel in the 4$\times$4 transform mode, while the two-stage pipelined architecture is used in the 8$\times$8 transform mode. Using 0.18-${\mu}{\rm m}$CMOS technology, the maximum operating frequency of the proposed multitransform architecture is 200 MHz, which achieves 4.1 Gpixels/sec throughput rate with the hardware cost of 63618 gates. Compared with existing designs, the proposed design delivers at least 54% higher throughput at 38% higher throughput/area ratio in Adaptive Block-size Transform (ABT) mode.

Complex software programs are mostly characterized by phase behavior and runtime distributions. Due to the dynamism of the two characteristics, it is not efficient to make workload predictions during design-time. In our work, we present a novel online DVFS method that exploits both phase behavior and runtime distribution during runtime in combined Vdd/Vbb scaling. The presented method performs a bi-modal analysis of runtime distribution, and then a runtime distribution-aware workload prediction based on the analysis. In order to minimize the runtime overhead of the sophisticated workload prediction method, it performs table lookups to the pre-characterized data during runtime without compromising the quality of energy reduction. It also offers a new concept of program phase suitable for DVFS. Experiments show the effectiveness of the presented method in the case of H.264 decoder with two sets of long-term scenarios consisting of total 4655 frames. It offers 6.6% ∼ 33.5% reduction in energy consumption compared with existing offline and online solutions.

H.264/AVC coders use the rate-distortion (R-D) cost function to decide the coding mode for each coding unit for better R-D tradeoff. To evaluate the R-D cost function, both the bit rate and the video quality degradation of the candidate mode must be calculated. In this paper, a fast context-adaptive binary arithmetic coding (CABAC) rate estimation scheme is proposed to accelerate the rate calculation. The speed of the proposed rate estimator depends only on the number of contexts used in the coding unit. Experimental results show that the proposed rate estimator reduces about 20% of the computational complexity of the R-D optimized mode decision when it is implemented as software. The entire encoder implemented as software is then accelerated by 16% with negligible degradation in the R-D performance. If implemented as hardware, the proposed scheme is expected to accelerate the rate estimation for a macroblock by 5 to 18 times faster than the conventional CABAC operation.

With a rapid increase of image resolution in recent mobile video systems, the memory bandwidth and power consumption have surfaced as critical problems in video coding. Despite many embedded compression algorithms proposed to overcome these problems, no proper algorithms have yet been reported with high enough throughput and no quality loss. This paper first proposes a lossless embedded compression algorithm with high compression ratio along with the hardware architecture for high throughput. Experimental results show that the proposed algorithm achieves at least 60% data compression without quality loss and bitrate increment. Moreover, the latency of the proposed architecture is sufficient to meet the real-time requirement of high-definition video coding, i.e., 30 cycles/macroblock. The proposed algorithm can be implemented with about 28 K gates.

In this paper, we propose a fast multi-layer motion estimation algorithm for spatial scalability provided in H.264/AVC scalable extension, based on the reuse of the motion vectors from multiple spatial layers. The reused motion vector is used to set a search center and refined within a small search area. However, the reused motion vector often produces significant prediction error at object boundaries. Motion vector difference defined in the H.264/AVC standard is used to decide whether the reused motion vector is appropriate. In addition, a search range is dynamically adjusted based on the distribution of the rate-distortion cost. By using the proposed multi-layer motion estimation, we reduce the execution time of motion estimation by almost 93% at the cost of 0.01 dB PSNR decrease and 0.79% bit-rate increase.

This paper presents a method to customize instruction-set for configurable multiprocessors under a given silicon area budget so that total dynamic energy consumption is minimized when dynamic voltage and frequency scaling (DVFS) is employed. The proposed method is based on Mixed-Integer Linear Programming (MILP) to select the optimal processor configurations for real-time tasks from custom instruction candidates. We have evaluated the proposed method using real-life applications and commercial configurable processors. The results show that the optimally configured multiprocessors by our method has up to 23.2% reduction of dynamic energy consumption in comparison with the multiprocessors configured by a conventional approach.

Dynamic voltage and frequency scaling (DVFS) for a parallel software program is crucial for lowering the ever-increasing power consumption of multiprocessor systems-on-chips (SoCs). In this paper, we propose an analytical DVFS method that judiciously exploits slack by considering the varying parallelism over each path in a task graph. The proposed method overcomes the conventional pessimistic assumption on the remaining workload, i.e., worst-case execution cycle. It yields minimum average energy consumption by utilizing the runtime distribution of a software program while satisfying the deadline constraints. The proposed method tackles leakage power consumption as well as dynamic power consumption by combinedVdd/Vbbscaling. Compared to conventional method , experimental results show that the proposed method provides up to 49.20% energy reduction for a set of synthetic task graphs and yields 23.93% and 27.15% energy reductions for two multimedia applications, namely, the H.264 encoder and decoder, respectively.

In motion estimation for video codec, reducing the amount of external memory access is critical to reduce power consumption and to minimize performance degradation. Previous search area reuse algorithms to reduce the memory access still suffer from coding efficiency degradation in fast motion video. Previously, we proposed a selective search area reuse (SSAR) algorithm to reduce the amount of external memory access with minimal coding efficiency degradation. In this letter, we extend SSAR algorithm to multiple reference frame motion estimation with a method to utilize multiple on-chip memories. Then, we propose a frame-level dynamic search range algorithm based on the SSAR algorithm. Finally, we propose a memory usage switching method to increase the utilization of the limited-size on-chip memory. Experimental results show that the proposed algorithm with a search range of 16 achieves 28.64-56.24% reduction according to the number of on-chip memories in multiple reference frames. In the results of the Foreman video sequence, our algorithm operating with a fixed-size on-chip memory compensated for quality degradation by up to 2.7 dB in the frames of fast camera motion, and reduced the amount of memory access by 22.6% with a peak signal-to-noise ratio gain of 1 dB in the frames of camera shaking.

In H.264/AVC decoder system, motion compensator (MC) is the most critical component in terms of computational complexity and memory access. We propose Data Reuse method between Heterogeneous Partitions (DRHP) to reduce the memory access of MC. Our method reuses data in the overlapped region between memory access regions of neighboring blocks in the different partitions as well as in the same partition. DRHP reduces memory access especially well at high-quality video stream and, without additional buffers, achieves up to 20.4% less memory access compared to the conventional scheme.

Dynamic voltage scaling (DVS) is a very powerful technique in reducing dynamic power consumption of CMOS circuits. Recent studies showed that intra-task DVS method which adjusts the voltage level during program execution can achieve significant energy reduction. However, the overhead of large number of voltage switching becomes a limitation for its practical implementation. In this paper, we propose a novel task partitioning algorithm for intra-task DVS which partitions a given task so that the DVS can be applied more effectively with the minimum number of voltage switching. Experimental result using H.264 decoder software shows that the proposed algorithm reduces the energy consumption by up to 25% over the conventional method.

This paper addresses a problem of modeling the power consumption of advanced off-the-shelf processors. Unlike existing methods for processor power estimation, where the internal information of processor architecture such as activation of specfic modules such as pipeline stages, etc.) is available via simulation or runtime counters, power modeling method presented in this paper is to estimate the power consumption of complex off-the-shelf RISC processor without such a detailed information, only based on the information of the processor I/O signals (i.e memory access). To tackle this problem, we propose a new power model, called IPI(Instruction-Prefetch Interval) power model. The IPI represents the time interval between two consecutive instruction prefetchs. Our model has two major advantages. First, this model can consider prefetch mechanism. Most of advanced RISC processors have prefetch mechanism which makes processor power estimation difficult. IPI model is the first approach to model prefetch mechanism in processor power estimation. Second, this model can provide power variation in time and therefore it overcomes the limitation of previous work, such as instruction-level energy model. Experiments show that the proposed model yields 96% accuracy on theaverage in case of ARM1136JF-S test chip.

Motion estimation has been widely studied and used to improve coding efficiency with small data access for power-saving. Conventional search area reuse algorithm requires small memory access by reuse of search area, but, suffers from coding efficiency degradation in fast motion video sequence. In this paper, we propose a search area selective reuse algorithm. The proposed algorithm well selects search center for reducing memory access in slow motion region and for tracking real motion in fast motion region according to the motion vector and search center information of the neighbor block. Compared to the conventional reuse algorithm, our experimental results show that the proposed algorithm prevents the coding efficiency degradation with small memory access overhead by tracking real motion in fast motion frames.

In this paper, a high-performance 2-D inverse transform architecture for the H.264/AVC decoder is proposed. The proposed architecture utilizes the block multiplication and permutation matrices. By applying permutation matrices, the IDCT matrix is regularized and the inverse Hadamard transform is merged into IDCT with a minor modification. The proposed architecture eliminates the data transpose register array to make the 2-D direct transform possible with the minimum latency of one clock cycle. When comparing the proposed design with existing designs, the proposed design has over 22% higher throughput for computing IDCT and inverse Hadamard transform. It also owns over 62% higher hardware efficiency through the measure of DTUA for computing IDCT and inverse Hadamard transform.

Reducing cache misses without increasing cache associativity is critical for reducing the power consumption and cache access time. This paper has focused on the stack of a program which often occupies more than half of total memory accesses (Calder, et. al., 1998). This paper, as a result, proposes so-called dynamic stack allocation where the stack pointer is shifted at run time to a memory location which is expected to cause least number of cache misses. We implemented the proposed scheme using so-called dynamic stack allocator (DSA) which consists of cache miss predictor (CMP) to compute cache miss probability based on least recently used (LRU) policy and stack pointer manager (SPM) to manage multiple stack locations. We also verified the proposed scheme with both FPGA and ASIC by using iNCITE and Dong-Bu electronics 0.18mum process, respectively. Experimental results show that dynamic stack allocation significantly reduces cache misses from 4% to 42% in various benchmarks with relatively small power consumption and no extra delay.

In this paper, we present the way of fast and accurate estimation of software energy consumption in off-the-shelf pro- cessor using IPI(Inter-Prefetch Interval) energy model. In our previous work[1], we proposed a new energy estimation method, and presented the way to characterize IPI energy model. However, there were some drawbacks in our previous work. First, the previous IPI energy model was only able to cover basic block. Second, it took too much time to estimate energy consumption of software due to the absence of energy estimator. To tackle these problems, in this paper, we propose modified IPI energy model, and present the way to implement IPI energy estimator using off-the-shelf system-level simulator. By using this, we can analyze such dynamic effect as address jump due to branch instructions and stalls due to hazard fast and accurately. The major challenging issue when implementing IPI energy estimator is cycle-by-cycle behavioral discrepancy between physical chip and ISS(Instruction Set Simulator) in system-level simulator. In order to overcome this problem, we propose training method to reduce the discrepancy. To verify our method, we applied our idea to ARM1136JF-S real chip. By the result of this work, the accuracy of energy estimation is more than 90% compared to measured data on prototyping board.

In this paper, a low-power deblocking filter architecture for H.264/AVC is proposed. A hybrid filtering order has been adopted to boost the speed of the deblocking filter process up to 208 clock cycles per 16x16 macroblock. The processing order of the filter is optimized to reduce power consumption and filter size and this is done by reducing memory access and raising the reusability of register blocks. A hardware implementation, under Samsung 0.18 μm standard cell library, consumes 18.34K gates at a clock frequency of 125MHz. Comparing to some state- of-the-art designs, the proposed architecture delivers the lowest level of power consumption while achieving similar speed of performance.

For system-level simulation of a complex system-on-chip design, multiple hardware simulators and emulators can be combined to work together. The simulation performance in this case is often limited by the communication overhead between simulators and emulators. To reduce the amount of communication in this heterogeneous simulation environment, we propose novel methods to find a time interval during which there are no transactions among simulators based on a dynamic prediction of transaction occurrence time for both software and hardware models. We also propose a simulator scheduling algorithm which allows the simulator to work alone without interaction with others when there is no transaction. By so doing, we reduced the amount of pure communication by a factor of 15 to 67 and, as a result, achieved a speed-up factor of 4 to 40 compared to existing lock-step simulation, as shown by experimental results with various application examples.

This paper presents a scheme called PrePack for suppressing the channel traffic between simulator and accelerator in the accelerator-based hardware/software co-emulation where the accelerator models some register transfer level (RTL) subblocks while the simulator runs transaction-level modeling (TLM) of the remaining part of the design under verification (DUV). With the conventional simulation accelerator, a cycle consisting of a pair of evaluations of simulator and accelerator occurs at every valid simulation time, which results in poor simulation performance due to the overhead of simulator–accelerator channel access, often accounting for more than 99% of total channel traffic time (total channel traffic time consists of channel-access time for arbitration/protocol exchange and pure data/signal transmission time). The overhead due to channel access can be reduced by merging as many channel transactions on the channel as possible into a single burst traffic, which is achieved in this paper by “prediction and rollback.” In the proposed “prediction and rollback” scheme, one of the two verification domains, i.e., software simulation and hardware acceleration, leads the other, while the leading domain predicts the states of the lagging domain. Therefore, the evaluation of simulator and accelerator no longer need to alternate at every simulation cycle. Under an ideal condition with 100% prediction accuracy, PrePack has shown a 15$times$speedup compared to the conventional scheme. When applied to advanced encryption standard (AES) and joint photographic experts group (JPEG) example systems, PrePack showed performance gains of 8.7 and 2.9, respectively.

This paper presents an optimized channel usage between simulator and accelerator when the simulator models transaction-level SoC while accelerator models RTL sub-blocks. Conventional simulation accelerators synchronize the progresses of simulator and accelerator at every simulation time, which results in poor performance by splitting transactions on the simulator-to-accelerator channel into pieces. Occasional synchronization with predictions and recoveries makes it possible to merge multiple transfers yielding substantial performance gain compared to the conventional method.

The paper presents a scheme for efficient channel usage between simulator and accelerator, where the accelerator models some RTL sub-blocks in the accelerator-based hardware/software co-simulation while the simulator runs a transaction-level model of the remaining part of the whole chip being verified. With conventional simulation, accelerator evaluations of simulator and accelerator alternate at every valid simulation time, which results in poor simulation performance due to the startup overhead of simulator-accelerator channel access. The startup overhead can be reduced by merging multiple transactions on the channel into a single burst traffic. We propose a predictive packetizing scheme for reducing channel traffic by merging as many transactions into a burst traffic as possible based on 'prediction and rollback'. Under ideal conditions with 100% prediction accuracy, the proposed method shows a performance gain of 1500% compared to the conventional one.

Simulation is the most viable solution for the functional verification of system-on-chip (SoC). The acceleration of simulation with multi-field programmable gate array (multi-FPGA) emulator is a promising method to comply with the increasing complexity and large gate capacity of SoC. Time multiplexing of interconnection wires is the inevitable solution to solve the pin limitation problem that limits the gate utilization of FPGAs and speed of multi-FPGA simulation accelerators. The most time-consuming factor of multi-FPGA simulation acceleration is the synchronization time between a software simulator and a multi-FPGA system and the inter-FPGA synchronization time. This paper proposes a performance-driven signal synchronization mechanism for a simulation accelerator with multiple FPGAs using time-multiplexed interconnection. The event-based signal synchronization optimizes the synchronization time between a software simulator and the multi-FPGA system as well as the synchronization time among FPGAs. The synchronization time among FPGAs is optimized by circuit partitioning considering the signal probability, net dependency reduction, and efficient net clustering to reduce addressing overhead. The synchronization time between the software simulator and the multi-FPGA system is also optimized by exploiting the event probability of primary nets. Experiments show that the synchronization time is reduced to 6.2-9.8% of traditional mechanisms.

This paper presents new technology that accelerates system verification. Traditional methods for verifying functional designs are based on logic simulation, which becomes more time-consuming as design complexity increases. To accelerate functional simulation, hardware acceleration is used to offload calculation-intensive tasks from the software simulator. Hardware accelerated simulation dramatically reduces the simulation time. However, the communication overhead between the software simulator and hardware accelerator is becoming a new critical bottleneck. We reduce the communication overhead by exploiting burst data transfer and parallelism, which are obtained by splitting testbench and moving a part of testbench into hardware accelerator. Our experiments demonstrated that the proposed method reduces the communication overhead by a factor of about 40 compared to conventional hardware accelerated simulation while maintaining the cycle accuracy and compatibility with the original testbench.

Functional coverage is a technique for checking the completeness of test vectors in HDL simulation. Temporal events are used to monitor the sequence of events in the specification. In this paper, automatic generation of temporal events for functional coverage is proposed. The HiTER is the graph where nodes represent basic temporal properties or subgraph and edges represent time-shift value between two nodes. Hierarchical temporal events are generated by traversing HiTER such that invalid, or irrelevant properties are eliminated. Concurrent edge groups make it possible to generate more comprehensive temporal properties and hierarchical structure makes it easy to describe large design by combining multiple subgraphs. Automatically enerated temporal events describe almost all the possible temporal properties of the design under verification.

Functional coverage is a technique which can be used for checking the completeness of test vectors. In this paper, automatic generation of temporal events for functional coverage is proposed. The TERG (Temporal Event Relation Graph) is the graph where the nodes represent basic temporal property and the edges represent the time-shift value between two properties. Hierarchical temporal events are generated by traversing TERG such that invalid or irrelevant properties are eliminated. Concurrent edge groups in TERG make it possible to generate more comprehensive temporal properties.

This work presents the automated process of translating behavioral testbench into synthesizable one for the hardware-accelerated simulation. Testbench is mainly implemented in unsynthesizable HDL description such as time delay, event control, non-static loops and sequential statements. Nonetheless, FPGA-based accelerator is limited to synthesizable design. To apply hardware acceleration to behavioral testbench, the proposed method automatically translates testbench into equivalent hardware by emulating the standard simulation reference model. By mapping testbench into hardware accelerator to be merged with the design under verification, we can accelerate behavioral testbench and remove the communication overhead between the software simulator and hardware accelerator. Our experiments demonstrated that the simulation time is reduced by a factor of about 1000 as compared to the conventional hardware accelerated simulation.

We present a new performance and routability driven routing algorithm for symmetrical array-based field-programmable gate arrays (FPGAs). A key contribution of our work is the overcoming of one essential limitation of the previous routing algorithms: inaccurate estimations of routing density that were too general for symmetrical FPGAs. To this end, we formulate an exact routing density calculation that is based on a precise analysis of the structure (switch block) of symmetrical FPGAs and utilize it consistently in global and detailed routings. With an introduction to the proposed accurate routing metrics, we describe a new routing algorithm, called cost-effective net-decomposition-based routing, which is fast and yet produces remarkable routing results in terms of both routability and net/path delays. We performed extensive experiments to show the effectiveness of our algorithm based on the proposed cost metrics.

FPGA-based logic emulator with large gate capacity generally comprises a large number of FPGAs connected in mesh or crossbar topology. However, gate utilization of FPGAs and speed of emulation are limited by the number of signal pins among FPGAs and the interconnection architecture of the logic emulator. The time-multiplexing of interconnection wires is required for multiFPGA system incorporating several state-of-the-art FPGAs. We propose a circuit partitioning algorithm called SCATOMi(scheduling driven algorithm for TOMi) for multiFPGA system incorporating four to eight FPGAs where FPGAs are interconnected through TOMi(time-multiplexed, off-chip, multicasting interconnection). SCATOMi improves the performance of TOMi architecture by limiting the number of inter-FPGA signal transfers on the critical path and considering the scheduling of inter-FPGA signal transfers. The performance of the partitioning result of SCATOMi is 5.5 times faster than traditional partitioning algorithms. Experiments on architecture comparison show that, by adopting the proposed TOMi interconnection architecture along with SCATOMi, the pin count is reduced to 15.2%-81.3% while the critical path delay is reduced to 46.1%-67.6% compared to traditional architectures including mesh, crossbar and VirtualWire architecture.

In this paper, we propose a scheme for reducing the power consumption of memory components by conforming memory contents to a precharging value. The scheme is oriented to application to single bitline structure of memory. It selectively stores normal or inverted data to reduce the number of bit accesses that have different values from the precharging value, which reduces overall bitline toggling and ultimately contributes to power reduction of the memory.

This paper presents an intellectual property (IP)-based system-on-chip (SoC) synthesis framework focusing on how to select IPs from different sources and how to integrate the selected IPs using on-chip buses. In order to synthesize an on-chip bus-based SoC architecture using IPs with imprecise design costs, we propose a possibilistic mixed integer linear programming (PMILP) model, which is converted into an equivalent mixed integer linear programming (MILP) model without increasing the computational complexity. Then, the equivalent MILP model is solved to decide whether each IP is selected or not, and to locate the selected IP on the optimal on-chip bus of a hierarchical bus architecture that consists of on-chip buses with different bus attributes. Experimental results on an MP3 decoding system show that the IP-centric design space with uncertainty can be successfully explored using the proposed scheme.

High-level synthesis using latches has many merits in power, area and even in speed. But latches cannot be read and written at the same time and usually requires two-phase non-overlapping clock that is unpleasant choice for short-term design. In this paper we propose a storage allocation method that makes it possible to use latches as storage elements in single clocking scheme. The proposed method modifies the lifetime of variables slightly so that it can be applied to any high-level synthesis systems with small modification. The experimental results show 39 ~ 65% reduction in power consumption within almost same area compared to the conventional power management scheme using clock gating.

Article Share on An accurate evaluation of routing density for symmetrical FPGAs Authors: Nak-Woong Eum Electronics & Telecommunications Res. Institute, Taejon, Korea Electronics & Telecommunications Res. Institute, Taejon, KoreaView Profile , Taewhan Kim Dept. of EECS, KAIST, Taejon, Korea Dept. of EECS, KAIST, Taejon, KoreaView Profile , Chong-Min Kyung Dept. of EECS, KAIST, Taejon, Korea Dept. of EECS, KAIST, Taejon, KoreaView Profile Authors Info & Claims GLSVLSI '01: Proceedings of the 11th Great Lakes symposium on VLSIMarch 2001 Pages 51–55https://doi.org/10.1145/368122.368794Online:01 March 2001Publication History 0citation151DownloadsMetricsTotal Citations0Total Downloads151Last 12 Months0Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

This paper presents a new performance and routability driven routing algorithm for symmetrical array based field-programmable gate arrays (FPGAs). A key contribution of our work is to overcome one essential limitation of the previous routing algorithms: inaccurate estimations of routing density which were too general for symmetrical FPGAs. To this end, we derive an exact routing density calculation that is based on a precise analysis of the structure (switch block) of symmetrical FPGAs, and utilize it consistently in global and detailed routings. With an introduction of the proposed accurate routing metrics, we design a new routing algorithm called a cost-effective net-decomposition based routing which is fast, and yet produces remarkable routing results in terms of both mutability and path/net delays. We performed an extensive experiment to show the effectiveness of our algorithm based on the proposed cost metrics.

Abstract — This paper presents a special hardware implementation developed for the computation of the specular term which is the most time consuming part in the Phong's illumination. In the Phong shading, the exponentiation operation of two floating-point numbers is necessary for each point inside a polygon. An approximation algorithm is developed to speed up the exponentiation operation, and it is supported by simple hardware that can be easily merged into a floating-point multiplier. The exponentiation operation takes just 4 cycles in the proposed hardware while it takes about 100-200 cycles in conventional floating-point units. Although an approximation algorithm is employed for the exponentiation operation, the amount of error is so minimal that the difference is virtually indistinguishable. I.

We propose a scheme for expanding switch modules to form a larger switch using the so-called local switching obtained by allowing bidirectional connection to the conventional three-stage Clos (1953) network switch. The performance of the proposed expansion architecture was compared to that of the conventional three-stage Clos network. We simulated 32/spl times/32 switching systems using two expansion architectures with the same switching strategy. Experiments show that the average switching latency is reduced by up to 60% in the expansion using the local switching network compared to one using the conventional three-stage Clos network switch. The latency reduction is dependent on the ratio of the delay of the switch fabric to that of the port controller. Expansion using the local switching network reduces latency across the switching system.

In system-on-a-chip design, interfacing of Intellectual Property (IP) blocks is one of the most important issues. Since most IPs are provided by different vendors, they have different interface schemes and different operating frequencies. In this paper, we propose a new interface synthesis method that enables one not only to handle the interface between IPs with different operating frequencies but also to minimize the hardware resource required for the interface. We have demonstrated the proposed algorithm by applying it to a real design example, MP3 decoder, and verified the IIS-to-PCI protocol converter on a real hardware system.

Texture mapping is a common technique used to increase the visual quality of 3D scenes. As texture mapping requires a large amount of memory to deal with large textures generally required in the current visual systems, we propose an algorithm for compressing a pyramid texture used for mipmapping. Vector quantization is used to compress all levels of the pyramid texture to one representative value databook, one residual codebook and one index map. The proposed compression scheme uses interpolative texel difference vector quantization that compresses the difference between the interpolated surfaces generated by the representative value and the correct uncompressed texels of the texture at each level. The compressed pyramid texture can be accessed randomly and decompressed without loss of visual quality. We also propose a hardware architecture that performs the trilinear filtering with the compressed pyramid texture.

This paper describes the MetaCore system which is an application-specific instruction-set processor (ASIP) development system targeted for digital signal processor (DSP) applications. The goal of the MetaCore system is to offer an efficient design methodology meeting specifications given as a combination of performance, cost, and design turnaround time. The MetaCore system consists of two major design stages: design exploration and design generation. In the design exploration stage, MetaCore system accepts a set of benchmark programs and structural/behavioral specifications for the target processor and estimates the hardware cost and performance for each hardware configuration being explored. Once a hardware configuration and instruction set are chosen, the system helps generate the target processor design in the form of hardware description language (HDL) along with the application program development tools such as C compiler, assembler, and instruction set simulator. The effectiveness of the MetaCore system was verified with a successful design of MDSP-II, a programmable DSP processor targeted for mobile communication.

We propose a new technique called node sampling to speed up the probability-based power estimation methods. It samples and processes only a small portion of total nodes to estimate the power consumption of a circuit. It is different from the previous speed-up techniques for probability-based methods in that the previous techniques reduce the processing time for each node while our method reduces the number of nodes actually processed. In addition, it is also different from the previous statistical sampling simulation techniques for simulation-based methods in that the previous methods sample the input vectors while our method samples the nodes in the network. The experimental results are very encouraging. The proposed method shows on the average more than 80% and 60% reductions of simulation run time under 20% and 5% error bounds, respectively.

We propose a new flip-flop configuration which saves about 60% of total clocking power using a half-swing clock. To use the half-swing clock, level converters or special clock drivers are traditionally required and the power consumptions of this logic cannot be ignored. In the proposed scheme, only NMOS devices are clocked with a half-swing clock in order to make it operate without the level converter or any other additional logics, and the random logic circuits except for the clock and flip-flops are supplied by V/sub cc/ while the clock network is supplied by V/sub cc//2. Compared to the conventional scheme, a great amount of power consumed in clocking which is responsible for a large portion of total chip power can be saved with the proposed new flip-flop configuration.

In this paper, we describe a fast and convenient verification method-ology for microprocessor using large-size, real application pro-grams as test vectors. The verification environment is based on automatic consistency checking between the golden behavioral ref-erence model and the target HDL model, which are run in an hand-shaking fashion. In conjunction with the automatic comparison facility, a new HDL saver is proposed to accelerate the verifica-tion process. The proposed saver allows 'restart ' from the nearest checkpoint before the point of inconsistency detection regardless of whether any modification on the source code is made or not. It is to be contrasted with conventional saver that does not allow restart when some design change, or debugging is made. We have proved the effectiveness of the environment through applying it to a real-world example, i.e., Pentium-compatible processor design process. It was shown that the HDL verification with the proposed saver can be faster and more flexible than the hardware emulation approach. In short, it was demonstrated that restartability with source code modification capability is very important in obtaining the short de-bugging turnaround time by eliminating a large number of redun-dant simulations. 1

The growing requirements on the correct design of a highperformance system in a short time force us to use IP's in many designs. In this paper, we propose a new approach to select the optimal set of IP's and interfaces to make the application program meet the performance constraints in ASIP designs. The proposed approach selects IP's with considering interfaces and supports concurrent execution of parts of task in kernel as software code with others in IP's, while the previous state-of-the-art approaches do not consider IP's and interfaces simultaneously and cannot support the concurrent execution. The experimental results on real applications show that the proposed approach is effective in making application programs meet the performance constraints using IP's.

Article A floorplan-based planning methodology for power and clock distribution in ASICs Share on Authors: Joon-Seo Yim DSP Group, Information Technology Lab., LG Corporate Institute of Technology, 16, Woomyeon-Dong, Seocho-Gu, Seoul, 137-140, Korea DSP Group, Information Technology Lab., LG Corporate Institute of Technology, 16, Woomyeon-Dong, Seocho-Gu, Seoul, 137-140, KoreaView Profile , Seong-Ok Bae DSP Group, Information Technology Lab., LG Corporate Institute of Technology, 16, Woomyeon-Dong, Seocho-Gu, Seoul, 137-140, Korea DSP Group, Information Technology Lab., LG Corporate Institute of Technology, 16, Woomyeon-Dong, Seocho-Gu, Seoul, 137-140, KoreaView Profile , Chong-Min Kyung Department of Electrical Engineering, KAIST, 373-1, Kusong-Dong, Yusong-Gu, Taejon, 305-701, Korea Department of Electrical Engineering, KAIST, 373-1, Kusong-Dong, Yusong-Gu, Taejon, 305-701, KoreaView Profile Authors Info & Claims DAC '99: Proceedings of the 36th annual ACM/IEEE Design Automation ConferenceJune 1999 Pages 766–771https://doi.org/10.1145/309847.310054Online:01 June 1999Publication History 34citation542DownloadsMetricsTotal Citations34Total Downloads542Last 12 Months12Last 6 weeks1 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

Article Reducing cross-coupling among interconnect wires in deep-submicron datapath design Share on Authors: Joon-Seo Yim DSP Group, Information Technology Lab., LG Corporate Institute of Technology, 16, Woomyeon-Dong, Seocho-Gu, Seoul, 137-140, Korea DSP Group, Information Technology Lab., LG Corporate Institute of Technology, 16, Woomyeon-Dong, Seocho-Gu, Seoul, 137-140, KoreaView Profile , Chong-Min Kyung Department of Electrical Engineering, KAIST, 373-1, Kusong-Dong, Yusong-Gu, Taejon, 305-701, Korea Department of Electrical Engineering, KAIST, 373-1, Kusong-Dong, Yusong-Gu, Taejon, 305-701, KoreaView Profile Authors Info & Claims DAC '99: Proceedings of the 36th annual ACM/IEEE Design Automation ConferenceJune 1999 Pages 485–490https://doi.org/10.1145/309847.309984Online:01 June 1999Publication History 37citation438DownloadsMetricsTotal Citations37Total Downloads438Last 12 Months1Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

This paper describes a core-customization process of a CISC processor core for a given application program. It aims at the power reduction in the CISC processor core by fully utilizing the microcode-based control scheme, that is one of the most characterizing features of a CISC processor The optimization process includes two key techniques, generation of application-specific complex instructions (ASCI) and low-power-oriented microcode-ROM compilation, which independently operate at the two different levels of optimization. As a means of architectural level of optimization, application-specific complex instructions are generated so as to reduce the activities of fetch and decode units, and in the point of physical level of optimization, the microcode-ROM is compiled to reduce the bit-line toggling for each microcode-ROM access. Our experimental results based on transistor-level simulation show the proposed techniques can jointly reduce the total power consumption of the CISC processor core by up to 41%.

A new parallel array multiplier based on a new circuit called a weighted carry-save adder (WCSA) is presented in this paper. Each row of the array consists of a (n+3) bit carry-save adder and one WCSA. Since the proposed WCSA enables the multiplier to be very regular as well as to have less operation complexity at the final addition stage than that of conventional implementations, the proposed WCSA is better suited for hardware implementation. Compared with the previous implementations, the proposed multiplier yields an area reduction of 21% for 64/spl times/64 multiplication. A 16/spl times/16 multiplier implemented in 0.8 /spl mu/m CMOS DLM technology functions at more than 60 MHz. The chip is 1.04/spl times/1.15 mm/sup 2/ with 7877 transistors.

In this paper, we propose a ' conforming inverted data store' scheme for reducing the power consumption in memory components.It reduces the power consumption by conforming memory contents to a precharging value of the memory.It selectively stores normal or inverted data so to reduce the total number of accessing bits different from the precharging value.In this way, bitline toggling during memory access is minimized and this ultimately contributes to a reduction in power consumption.We develop two practical implementations for the proposed method, that are vertical strip, and horizontal strip inversion schemes.Simulation results indicate that implementation of the strip-based inversion schemes contribute to a power reduction up to 50%.

Application specific instructions play an important role in reducing the required code size and increasing performance in embedded DSP systems. This paper describes a new approach to generate application specific instructions for DSP applications. The proposed approach is based on a modified subset-sum problem and supports multicycle complex instructions, as well as single-cycle instructions, while the previous state-of-the-art approaches generate only the single-cycle instructions or just select instructions from the fixed super-set of possible instructions. In addition, the proposed approach can also be applied to the case that instructions are predefined. Experimental results on real applications show that Various given constraints can be met by the generated set of application specific instructions without attaching special hardware accelerators.

The design of application-specific processor for DSP applications is not only driven by low-cost requirements, but also needs to fulfil constraints in terms of short development time. MetaCore, a configurable and instruction-level extensible DSP core, can effectively satisfy these requirements by providing a high degree of customization to the given application. In this paper, we present architectural concept of MetaCore and the MetaCore development platform. And we also present the first-generation MetaCore product version, MDSP16, which is a 16-by-16 fixed-point DSP processor. MDSP1.6 was implemented using 0.6 /spl mu/m TLM CMOS technology and has 50 MIPS peak performance.

As design complexity increases, functional verification becomes a crucial issue to ensure design correctness at an early design stage. Traditional methods for verifying functional designs are based on the HDL simulation, which is becoming the bottleneck of the design cycle because of the increasing design complexity. The accurate verification ability at the architectural level through a large set of the test programs and real world applications is a foundation for the next design step. In this paper, we describe how to verify a functional model on a real target system. The proposed methodology called virtual chip makes it possible not only to check the functional correctness on real systems, but also to explore design space by measuring the performance effectiveness of various architecture parameters under real applications. Experimental results show that functional models can be verified on real systems using complicated application programs. The proposed functional verification method is faster than HDL simulation and even comparable to emulation.

This paper describes the MetaCore system which is an ASIP (Application-Specific Instruction set Processor) development system targeted for DSP applications. The goal of MetaCore system is to offer an efficient design methodology meeting specifications given as a combination of performance, cost and design turnaround time.

In this paper, we present an approach to synthesize multiple behavior modules. Given n DFGs to be implemented the previous methods scheduled each of them sequentially, and implemented them as a single module. Though the method Is appropriate for sharing the functional units, it ignored the following two aspects: (1) different interconnection patterns among DFGs can increase the interconnection area and delay of the critical path, (2) the sequential scheduling of DFGs has a difficulty in considering the effects on the other DFGs not scheduled yet. We show an efficient way to solve the problems using a selective grouping method and the extensions of the traditional scheduling methods. The experimentation reveals that the result obtained by the proposed method is better to reduce interconnection area and to meet the timing constraints than those obtained by the previous methods.

Article Free Access Share on Synthesis of application specific instructions for embedded DSP software Authors: Hoon Choi Department of Electrical Engineering, Korea Advanced Institute of Science and Technology, Taejon, Korea Department of Electrical Engineering, Korea Advanced Institute of Science and Technology, Taejon, KoreaView Profile , Seung Ho Hwang Department of Electrical Engineering, Korea Advanced Institute of Science and Technology, Taejon, Korea Department of Electrical Engineering, Korea Advanced Institute of Science and Technology, Taejon, KoreaView Profile , Chong-Min Kyung Department of Electrical Engineering, Korea Advanced Institute of Science and Technology, Taejon, Korea Department of Electrical Engineering, Korea Advanced Institute of Science and Technology, Taejon, KoreaView Profile , In-Cheol Park Department of Electrical Engineering, Korea Advanced Institute of Science and Technology, Taejon, Korea Department of Electrical Engineering, Korea Advanced Institute of Science and Technology, Taejon, KoreaView Profile Authors Info & Claims ICCAD '98: Proceedings of the 1998 IEEE/ACM international conference on Computer-aided designNovember 1998 Pages 665–671https://doi.org/10.1145/288548.289109Published:01 November 1998Publication History 18citation223DownloadsMetricsTotal Citations18Total Downloads223Last 12 Months16Last 6 weeks2 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

The authors describe the implementation and design methodology of a microprocessor, called HK386. The microprocessor is compatible with Intel 80386 with respect to the behavior of each instruction set. As the extraction of the exact behavior of each instruction set is the single most important step in compatible chip design, they focused their effort on establishing the reliable verification strategy ensuring the complete instruction level compatibility. The HK386 was successfully designed and fabricated using 0.8 /spl mu/m CMOS technology.

This paper describes the current status of multi-project chip (MPC) services in Korea to promote full-custom and semi-custom IC design activities in universities. Although MPC foundry services for IC designs were started in a lesser scale more than 10 years ago, it is only recently that systematic and effective education has developed. The MPC foundry services program called IDEC (IC design education center) was launched with the planned support of the government and three major semiconductor companies in Korea. The paper introduces the activities of IDEC and other MPC foundry services.

Proposes the CBLO (clustering-based linear ordering) algorithm, which consists of both global ordering and local ordering. In the global ordering, the algorithm forms clusters from n given vertices and orders the clusters. In the local ordering, the elements in each cluster are linearly ordered. The linear order thus produced is used to obtain optimal k-way partitioning based on a scaled cost objective function. Experiments with 11 benchmark circuits for k-way (2/spl les/k/spl les/10) partitioning showed that the proposed algorithm yields an average of 10.6% improvement over MELO (multiple-eigenvector linear ordering) for k-way scaled cost partitioning.

In microprocessors, reducing the cache access time and the pipeline stall is critical to improve the system performance. To overcome the pipeline stall caused by the misaligned multi-words data or multi cycle accesses of prefetch codes which are placed over two cache lines, we proposed the Separated Word-line Decoding (SEWD) cache. SEWD cache makes it possible to access misaligned multiple words as well as aligned words in one clock cycle. This feature is invaluable in most microprocessors because the branch target address is usually misaligned, and many of data accesses are misaligned. 8K-byte SEWD cache chip consists of 489,000 transistors on a die size of 0.853/spl times/0.827 cm/sup 2/ and is implemented in 0.8 /spl mu/m DLM CMOS process operating at 60 MHz.

As the complexity of high-performance microprocessor increases, functional verification becomes more difficult and emerges as the bottleneck of the design cycle. In this paper, we suggest a functional verification methodology, especially for the compatible microprocessor design. To guarantee the perfect compatibility with previous microprocessors, we developed three C models in different representation levels, i.e., Polaris, MCV(Micro-Code Verifier) and StreC. C models are co-simulated with consistency checking between two different models. The simulation speed of C models makes it possible to test the "real-world" application programs on the RTL design with a software board model. To increase the confidence level of verifications, Profiler reports the verification coverage of the test vector, which is fed back to the automatic test program generator. Restartability feature also helps significantly reduce the total simulation time. Using the proposed verification methodology, we designed and verified an Intel 486-compatible microprocessor successfully.

As the complexity of high-performance microprocessor increases,functional verification becomes more and more difficultand RTL simulation emerges as the bottleneck of thedesign cycle.In this paper, we suggest C language-based designand verification methodology to enhance the simulationspeed instead of the conventional HDL-based methodologies.RTL C model (StreC) describes the cycle-based behaviors ofsynchronous circuits and is followed by model refining andoptimization using LifeTime Analyzer (LTA) and Cleaner.The simulation speed of cycle-based C model makes it possibleto test the RTL design with the "real-world" applicationprograms in the order-of-magnitude faster speed thanthe commercial event-driven simulators.Using the proposedfunctional verification methodology, HK486, an intel 80486 - compatiblemicroprocessor was successfully designed and verified.

In the design of microprogrammed processors, the minimization of microcode width is very crucial to reduce the required microcode ROM area. The paper suggests two different procedures which are complementary in nature: first an integer linear programming formulation which guarantees an optimal solution for small or medium size problems; and second, a heuristic algorithm based on the graph bipartitioning to deal with large size problems. Experimental results show that the proposed heuristic algorithm yields near-optimal solutions with polynomial time complexity.>

FAMOS, an iterative improvement scheduling algorithm for the high-level synthesis of digital systems, is described. The algorithm is based on a move acceptance strategy and various selection functions defined to represent the cost of hardware resources such as functional units and registers. A main feature of the algorithm is that it can escape from local minima. The algorithm can deal with diverse design styles such as multi-cycle operations, chained operations, pipelined datapaths, pipelined functional units and conditional branches. Register costs and maximal time constraints are also considered. To efficiently represent information on the design styles, a graph model called weighted precedence graph is proposed as a general model on which the scheduling algorithm is based. Despite the iterative nature, the proposed algorithm has a polynomial time complexity. Although the optimality of the algorithm is not guaranteed, optimal solutions were obtained for several examples available from the literature.>

An algorithm, called self-organization assisted placement (SOAP), for circuit placement in arbitrarily shaped regions, including two-dimensional (2-D) rectilinear regions, nonplanar surfaces of three-dimensional objects, and three-dimensional volumes, is presented. SOAP is based on the self-organizing which adjusts the weight of synapses connected to neurons such that topologically close neurons become sensitive to inputs that are physically similar. A standard cell placement method and a global placement method of macro cells using SOAP algorithm are described. Several examples showing the circuit placement on rectilinear regions, nonplanar surfaces, and 3-D volumes are shown. Experimental results on benchmark circuits show that the SOAP algorithm is competitive with the state-of-the-art algorithms even for the case of placement in a rectangular region, which is a special case of a 2-D rectilinear region.>

A standard cell placement procedure that is based on an efficient global placement strategy, called HALO (hierarchical alternating liner ordering), is proposed. This method generates a global 2D placement of circuit modules by hierarchical application of linear ordering in an alternating direction. The HALO global placement procedure is followed by a detailed placement procedure which consists of row assignment, feed-through cell assignment and intrarow cell assignment steps. Experimental results on two benchmark circuits, primary1 and primary2, consisting of 752 and 2907 cells, have shown decreases of the half-perimeter routing lengths by 7% and 24%, respectively, compared with the best available results obtained so far. Total CPU time, including the subsequent detailed placement, was less than half that of previously published work.>

A new heuristic scheduling algorithm which has a feature of escaping from local minima is presented.The algorithm has a polynomial time complexity in spite of its iterative nature.Although there is no guarantee for the optimality, the algorithm produced optimal results for the experimental examples of earlier works.A graph model which contains information on the real world constraints such as multi-cycle operations, chained operations and pipelined data paths is also proposed as a general model on which our scheduling algorithm is based.

The authors propose a novel floorplanning algorithm which handles a mixture of fixed-shaped and variable-shaped blocks in a chip having a chip aspect ratio within a given range. This algorithm consists of two stages. In the first stage, overlapped blocks in the initial placement obtained using FDR (force directed relaxation) are spread out uniformly over the whole chip area using the ratioed rectangular Voronoi diagram such that each block finds enough space without significant overlap with its neighboring blocks. In the second stage, each block is reshaped or moved by the independent move of each block edge according to the attractive force and repulsive force exerted on it due to the overlap and the dead space, respectively. Experimental results were obtained on the ami33 benchmark circuit with varying conditions on the aspect ratio of blocks and chip. Significant improvement of the chip utilization factor has been obtained compared to previous work.>

The authors address the problem of minimizing the control ROM width, which is important in the design of microprogrammed processors, because it directly reduces the silicon area of the control unit. A heuristic algorithm is proposed which is based on graph partitioning. This algorithm results in nearly optimal solutions with the time complexity of O(n/sup 3/log n), where n denotes the number of distinct microoperations. Comparison of the results with earlier works shows that the proposed heuristic performs better in terms of cost and/or CPU time.>

A description is presented of a novel optimization procedure called diffusion which can be used in global circuit placement for suppressing inter-module and module-to-chip boundary overlaps. A salient feature of the proposed diffusion procedure is that multiple decisions on the moves of all variables (module positions) are simultaneously made such that a global, analytic objective function is minimized. Various strategies are discussed to speed up the convergence, and to prevent the solution from being stuck at local minima. A net force model is used with the diffusion procedure to minimize the inter-module wire length besides reducing the inter-module and module-to-chip overlaps. Various experimental results are given. Further potential applications of the proposed procedure include multilayer placement, and placement in an arbitrarily-shaped region.>