This paper presents an automated partitioning strategy to divide a design into a set of partitions based on design hierarchy information. While the primary objective is to use these partitions in an incremental design flow for compile time reduction, the performance of the partitioned design should not be degraded after partitioning. Experimental results using the incremental design feature of Altera's Quartus tool show that our algorithm can generate partitioning solutions comparable with a set of manually partitioned industrial circuits and results in more than 50% compile time reduction

This work presents a simultaneous sequential retiming and clustering algorithm for delay minimization applicable to FPGAs. The algorithm is based on Pan et al.(1998) with several modifications and enhancements to improve the performance of the final clustered circuits. A duplication control strategy is used to reduce the amount of node duplication. Experimental results on the biggest MCNC benchmark circuits using Altera's Quartus show that our algorithm can increase the performance, on average, by almost 22% compared with the case when Quartus is used without our clustering information.

We present an effective recursive algorithm for circuit clustering for delay and area minimization, which is applicable to FPGAs. At the highest level of clustering, the circuit is clustered using a modified single-level clustering algorithm. A cluster to netlist transformation technique is proposed, which converts each cluster into a new subcircuit. The algorithm then continues recursively by clustering the generated subcircuits into further levels of clusters. To reduce the amount of node duplication and the number of clusters at each level of clustering, we propose a node removal algorithm based on the node slack along with a simple cluster-packing algorithm. Experimental results on the two-level clustering problem using Quartus Design System from Altera show that our algorithm achieves, on average, 7.3% more delay reduction when compared to the latest published work on the problem. Also total FPGA compile time reported by Quartus is reduced by 36%.

This paper presents an effective algorithm for multi-level circuit clustering for delay minimization, which is applicable to FPGAs. At the highest level of clustering, the circuit is clustered using a modified single-level clustering algorithm. A cluster to netlist transformation technique is proposed, which converts each cluster into a new subcircuit. The algorithm then continues recursively by clustering the generated sub-circuits into further levels of clusters. To reduce the amount to area overhead, a node duplication control algorithm based on the node slack is proposed and a cluster packing algorithm is used to reduce the number of clusters. Experimental results on the two-level clustering problem using Quartus Design System from Altera show that our algorithm reduces the delay, on average, by 7.3% compared with the best results in. Also the total FPGA compile time for all the benchmark circuits reported by Quartus is reduced by 36%.

Although delay driven clustering algorithms can optimize circuit delay, they usually result in huge area increase. We present a node duplication control strategy along with a simple packing algorithm that greatly reduce the area penalty with a very small degradation in performance. We use the Quartus Design System from Altera to test our algorithm for a set of MCNC benchmark circuits. The results show that while a 14.5% average delay decrease can be achieved with an average area increase of 240.8%, the algorithm reduces the average area penalty to 27.4% with an average delay decrease of 13.8%. Also the number of clusters and the fitting time reported by Quartus are reduced by more than 91% and 60%, respectively.