Multiplier-accumulator (MAC) is a crucial arithmetic element widely used in digital integrated circuits. Customized MACs are necessary for different scenarios but need great effort due to the huge architecture design space. In this paper, we develop EasyMAC, a flexible Chisel-based MAC generator with a canonical architectural representation. We design a compact and canonical sequence representation to express the architecture of MACs. And the MAC generator takes the compact representation as input to gain the Verilog codes. We also give a case study on developing a heuristic design space exploration (DSE) method based on this representation. The experimental result shows the effectiveness of the representation in DSE. Using the percent relative range of the power-delay-area product as a metric to measure the optimization opportunities that this representation exposes, the relative range is 17.4% and 23.1% for 16×16 and 25×18 MACs, respectively. At last, we discuss some promising directions of EasyMAC.

Modern heterogeneous multi-processor system-on-chips (SoCs) have diverse needs of area, performance, and scalability for on-chip networks (OCNs). And it remains a challenge to design, evaluate, and explore a suitable OCN for a specific SoC to meet different requirements. Some open-source OCN generators have been developed to generate synthesizable RTL codes, provide fast testing, and enable design space exploration. However, none of them provides the levels of abstraction to trade off the various needs.In this paper, we propose Purlin, a versatile toolkit for the generation and simulation of OCNs. We put forward a uniform network generation and simulation flow across distributed routing, source routing, and circuit-switched OCNs to enable effective trade-offs. Purlin enables network customization through the network basic, flow control, and routing function interfaces and provides some predefined architectures. Among the architectures, the latency-optimized distributed routing OCN reduces 79.3% latency compared to a state-of-the-art OCN generator. With the routing function customization interface, we implement a deadlock-free adaptive routing function in the library, which reduces 16.1% latency. We provide compilation tools with customizable routing algorithms to generate the packet headers in source-routing or the configurations in circuit-switched OCNs from a programmed destination address. A source routing OCN using a customized routing algorithm further reduces 8.4% latency compared to a distributed routing OCN.

Coarse-grained reconfigurable architecture (CGRA) is a promising programmable device with high performance and power efficiency. The CGRA compilation problem is to map an application onto a 3D time-space model of CGRA. Adding the circuitry of synchronizers can relax the mapping constraint for data alignment in time; and thus, it significantly influences the compilation performance. However, data-departure synchronizers may be infeasible, because an output value may be used multiple times and has a high fan-out. Instead, data-arrival synchronizers can further improve performance and mappability of CGRAs with acceptable overhead, compared to the synchronization methods based on detour routing, register files, and FIFO.In this work, we design two kinds of data-arrival synchronizers and formulate them in an integer linear programming (ILP) based mapping approach. The separate ILP formulations of placement and routing speed up the architecture exploration with synchronizers by up to 3.03x. The experimental study shows that data-arrival synchronizers improve CGRA performance by 19.8% on average. The results of our quantitative study show that synchronizers also improve the mapping success rate by 1.91x on average. In conclusion, CGRAs with appropriate synchronizers have better mappability while using fewer resources.